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Posts Tagged ‘SoC integration’

#53DAC, 7: Fly brains, trillion-transistor devices and tales from a Steve Jobs alum

Tuesday, April 26th, 2016

All of a sudden it’s nearly the end of April, high time to switch from months to weeks (just six to go now!) in the countdown to DAC, which I can guarantee is going to be a great conference. One big reason I’m confident is that, as always, we have an excellent lineup of keynoters as worthy of a stage at TED or SxSW as at the world’s premier design automation conference. See my past posts on Peter Stone (Thursday keynote) and Lars Reger (Monday) for a refresher. And don’t forget the luminaries sandwiched between the two of them:

Tuesday back-to-back big thinkers will take the main stage. One is Louis Scheffer, a researcher at Howard Hughes Medical Institute. Shcheffer has spent a lifetime studying whether it might be possible to reconstruct the nervous system, a challenge given the boggling complexity in even the simplest animals. The humble fly brain that Scheffer studies has about 100 million connections. The success of Scheffer and his colleagues in mapping a small fraction of those connections, the region of the fly’s brain that processes vision, warranted a 2013 publication in Nature, likely the world’s most prestigious scientific journal.

#53DAC, 6: How long until you can take a self-driving car to DAC?

Monday, April 4th, 2016

NXP Automotive CTO Lars Reger to open DAC Monday; time to register and book your hotel | There is no hotter topic in tech than self-driving cars. How else to explain the worldwide headlines after what can only be described as a modest little fender-bender last month in Mountain View. The culprit was one of Alphabet, Inc.’s autonomous Lexus 450hs, by now a media darling/goat. Despite the apparent and very prosaic facts — the Lexus was traveling 2 miles per hour, nobody was hurt, it was the first at-fault incident in more than 1.5 million miles of autonomous driving, etc. — the event was and remains a modest sensation, online and otherwise.

“Google was dealing with a pronounced shadow hanging over its presence at SXSW this week,” wrote Nick Statt last week in The Verge. “Now the fallout [from the accident] has found its way into nearly every transportation-focused panel discussion here in Austin.”


IP Cuts Dynamic Power Dissipation 20% More Than Can Be Achieved With Standard Techniques

Tuesday, January 26th, 2016

CC-100 PowerOp IP 

The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile.  This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.

In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.

The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.

The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF   Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.


The Concurrent Design-Flow Experiment

Wednesday, August 8th, 2012

At DAC this year I had a lot of fun doing a live experiment to demonstrate some of the benefits and issues with concurrent design flows.  I was at the Cadence Theatre doing a presentation called ‘Controlling the costs of SoC integration‘ and I decided to make the presentation more interactive by creating a design team and seeing some of the effects of getting this team to work concurrently.  We demonstrated how a little ‘twist’ caused a big upset for to team deliveries!



The topic I introduced first was how system design flows are now highly concurrent.  In the production of a system within a very tight timescale, it would be normal to have architecture definition, software development, virtual prototype development, RTL design and verification all happening at the same time, be it IP, sub-system or SoC level design. I represented this as a set of rotating, interacting cogs.


S2C: FPGA Base prototyping- Download white paper

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