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 Guest Blogger
Oz Levia
Oz Levia
VP of Marketing and Business Development, Jasper Design Automation

Addressing the Challenges with SoC Integration and Verification

 
June 20th, 2013 by Oz Levia

As a society entrenched in connectivity, we put a great deal of pressure on our portable electronic devices to provide us with more and more computing power and capabilities.  Take this blog for example.  As I’m traveling, I’m actually writing this blog post on my smart phone. To write this effectively, I need to be able to easily flip back and forth between PowerPoint, Word, and the Internet while still answering emails and the occasional phone call.  The fact that my mobile device is able to handle all of these requests with no errors is astonishing given that just a few short years ago, this idea was just “pie in the sky”.  The computation complexities that make this possible are staggering.  But what is also staggering, is that even more complex designs are being created in ever shrinking time-to-market windows.  How do system and SOC companies remain competitive with these seemingly unrealistic expectations?

There are, of course, a myriad of answers to that question, but a critical facet is the use of third-party IP.  More and more companies must adopt third-party IP so that they can focus their design on their companies’ core competence.  Outsourcing other, proven, capabilities to IP providers saves a great deal of time, energy, and money.  However, the use of this third-party IP also introduces new challenges for interface specification, integration, and verification of SoCs on a large scale.  These challenges, if not addressed properly, can eliminate any of the productivity gains thought to be realized with the use of third-party IP.

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TSMC Ecosystem Moving Online

 
June 13th, 2013 by Tom Quan

There has been a great proliferation in the quantity and quality of online resources for IC designers over the past two decades.  This expanding set of options benefits both the designers and ecosystem partners such as foundries, tool vendors and IP suppliers.

For intellectual property (IP), multiple established sites deliver IP cataloging, news, planning and aggregation, and consulting.  These useful services come from established providers like ChipEstimate, Design & Reuse, and Silicon-IP.  Providing fast access to detailed information on thousands of IP alternatives helps build the market for IP innovators while providing designers with myriad technology solutions.

Web-based EDA solutions are also becoming more mainstream.  Many are ideally suited to the advantages that only online resources can deliver.  Examples include Cadence’s hosted design solution, Mentor’s thermal analysis, Synopsys’ logic verification and Nimbic’s electromagnetic analysis.  With seemingly unlimited compute power residing “in the cloud,” designers can have on-demand access to these types of scalable tools, eliminating constraints on their productivity.

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Using Formal Tools to Improve the Productivity of Verification at STMicroelectronics

 
April 9th, 2013 by Rob van Blommestein

At this year’s ChipEx, STMicroelectronics (ST) will discuss how they used formal methods as a means to improve the productivity of their verification. In particular, they had three key aims:

  1. To close verification projects with appreciably less time and effort than that required by a constrained random approach;
  2. To promote a greater use of assertions by encouraging designers to develop formal properties for their blocks;
  3. To augment or replace legacy in-house flows with mature industry tools. This reduces maintenance overhead and promotes a more robust approach.

They applied formal methods at the unit-level, block-level and the system-level of an ARM based CPU sub-system (see Figure 1). Each project gave different insights into the effectiveness of the formal approach. In order to make an effective evaluation, they developed constrained random alternatives. This allowed them to make direct comparisons and reduced the project’s risk.

A paper at ChipEx will be presented that describes the productivity improvements they experienced using formal methods to verify a critical CPU sub-system that is targeted at mobile applications. In particular, they describe the challenges involved and how a formal tool (Jasper) delivered benefits in terms of effort savings, re-use and insight into IP that was not fully characterized in the context of a new design. The full presentation will also describe their experiences using formal in the context of low-power verification, control status register checking and sequential equivalence.

Figure 1: An ST ARM based CPU sub-system. The shaded blocks were verified using Jasper.

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Get Powered Up with Formal Low Power Verification!

 
March 11th, 2013 by Rob van Blommestein

We as consumers want more functionality from our electronic devices whether from our smart phones or household appliances.  The problem that we create from these functionality demands is not only an increase in power consumption, but also a significant increase in complexity for how the power in these devices is managed.  We as consumers don’t often think about these consequences, but your typical electronic design engineer certainly does.

Today’s electronic designs require that power management and reduction be a central concern throughout the chip design flow from architectural design to RTL implementation and physical design.  The power verification dilemma is two-fold.  Not only must the design and verification engineer address whether or not the inserted power management circuitry functions correctly, but also that the overall chip functionality is not corrupted by the power intent described in the UPF or CPF descriptions.

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Silicon Valley veterans and experts accept young engineers as one of their own, at DesignCon, make them feel at home

 
February 5th, 2013 by Shachi Nandan Kakkar

When I, a high school senior, got an invite to be a panelist at a panel discussion on “Engineering The Next Generation”, I was a bit surprised.  I aspire to be an electronics or a computer engineer, but have still not entered College.  My dad, Sunil Kakkar who founded a chip design and verification company SKAK Inc., serves on the technical program committee of DesignCon, told me that electronic design and semiconductor experts from all over the world will come to participate in the conference that will run for 4 days.  The conference would be a high tech affair, so I would have to be technical in presenting my thoughts.  I was somewhat apprehensive.  Will he be able to get their attention – I thought?   Could I speak on topics which will make sense to them?  What will their reaction be, on a high school senior fromCupertinoHigh Schoolparticipating in the DesignCon conference?

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Oscillating microscopic beads could be key to biolab on a chip

 
September 25th, 2012 by Sanjay Gangal

Written by David Chandler, MIT News Office

MIT team finds way to manipulate and measure magnetic particles without contact, potentially enabling multiple medical tests on a tiny device.

If you throw a ball underwater, you’ll find that the smaller it is, the faster it moves: A larger cross-section greatly increases the water’s resistance. Now, a team of MIT researchers has figured out a way to use this basic principle, on a microscopic scale, to carry out biomedical tests that could eventually lead to fast, compact and versatile medical-testing devices.

The results, based on work by graduate student Elizabeth Rapoport and assistant professor Geoffrey Beach, of MIT’s Department of Materials Science and Engineering (DMSE), are described in a paper published in the journal Lab on a Chip. MIT graduate student Daniel Montana ’11 also contributed to the research as an undergraduate.

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The Concurrent Design-Flow Experiment

 
August 8th, 2012 by David Murray

At DAC this year I had a lot of fun doing a live experiment to demonstrate some of the benefits and issues with concurrent design flows.  I was at the Cadence Theatre doing a presentation called ‘Controlling the costs of SoC integration‘ and I decided to make the presentation more interactive by creating a design team and seeing some of the effects of getting this team to work concurrently.  We demonstrated how a little ‘twist’ caused a big upset for to team deliveries!

I1

Concurrency

The topic I introduced first was how system design flows are now highly concurrent.  In the production of a system within a very tight timescale, it would be normal to have architecture definition, software development, virtual prototype development, RTL design and verification all happening at the same time, be it IP, sub-system or SoC level design. I represented this as a set of rotating, interacting cogs.

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Is “Lifecare” the Next Killer App?

 
August 7th, 2012 by Jonah McLeod

Article source: Kilopass Technologies

The world population hit 7 billion last fall, with a billion more expected in a dozen years. “Lifecare” represents an incredible opportunity for the semiconductor industry to promote health, energy conservation, safety and productivity. From smart city infrastructure to medical care advances, from sensors and controls to nanotechnology, what new EDA ecosystems will emerge to better model the real world? Panelists participating in the discussion “Is Lifecare the Next Killer App?” at the Design Automation Conference on June 4, 2012 addressed the question and their remarks are quite enlightening. Moderator Rick Merritt, Editor at large, Electronic Engineering Times led the discussion, which included Kristopher Ardis from Maxim Integrated Products, Fabrice Hoerner, from QUALCOMM Inc. and Greg Fawcett from Palo Alto Research Center.

Accelerating Coverage Closure with Jasper

 
August 6th, 2012 by Rob van Blommestein

Jasper’s formal technology has advanced to the point that it can address a broad range of verification and design issues. With a strong foundation in fundamental proof technology and best-in-class capacity and performance, Jasper’s users now apply the tools and technology to address questions of connectivity, x-propagation, clock-glitch detection, protocol cache coherence, deadlock detection, property synthesis and more.

The added scope and breadth of use of Jasper’s tools and technology is leading users to demand a measurable and quantitative approach that will help correlate the results of formal proofs to verification closure, often expressed in terms of verification coverage. What is needed is a methodology that will correlate formal proof results with coverage. A second requirement is for a methodology that can integrate the coverage results from Jasper’s formal technology with other verification tools (simulation). A third requirement is the ability for Jasper tools to use external coverage data to address areas in the design that are not covered by other verification methodologies.

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Jasper Users Share How They Upgraded Their Verification with Jasper

 
August 1st, 2012 by Rob van Blommestein

Enough can’t be said about the power to educate based on experience.  At this year’s DAC, a few of Jasper’s top users volunteered to give seminars on their best practices for using Jasper Formal technology.  If you happened to miss DAC or did attend but didn’t get a chance to visit the Jasper booth, here’s your chance to view the on-line videos from ST, ARM, and NVIDIA on how they utilized Jasper Formal technology to get ahead in their designs.

ST: Low Power Verification and Optimization with Jasper Formal

ST Microelectronics talked about the verification challenges associated with sophisticated low-power designs, and ways those challenges are being addressed by Jasper’s power-aware formal verification technology.  The seminar detailed how Jasper’s low-power verification solution applies to:

  • Parsing CPF information to enable power-aware formal analysis
  • X-propagation due to shutting down power
  • Functional impact due to power-down
  • Power-up state analysis
  • Exploration of power-state

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