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Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More »

Rapid Custom Digital Cell Layout with the Symbolic Editor

 
November 3rd, 2016 by Graham Etchells, Director of Product Marketing at Synopsys

In the ‘Custom Compiler Layout Assistants (Part 1)’ blog post, I profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern (for example, a differential pair) very easy. With no constraints to enter and no code to write, layout is done in minutes vs. hours.

However, there is a lot more to the symbolic editor than the ability to simplify interdigitation. One good example is the ability to define multiple P and N row pairs and then symbolically chain and fold the transistors such that you get them to fit neatly in the rows. This is a key feature that allows you to not only control the aspect ratio of the design, but to very rapidly create a custom digital cell layout, as shown in Figure 1.

SED_Multi_2_croppped

Figure 1. Multiple Row Pairs

Custom Compiler’s symbolic editor can also be used in conjunction with a cell template. The cell template provides a graphical way of defining the topology of your layout and, in the case of digital standard cell design, provides a consistent base topology as the common starting point. With the cell template you can define where your power and ground rails are in relation to the P and N channels, as well as the spacing between the P and N channels and other topology variables such as power and ground rail widths. The template can be modified to suit your needs and then saved off for future use by other layout designers.

Using the symbolic editor allows layout engineers to make simple graphical choices of how the layout needs to look and then have the detailed placement taken care of by the placement engine. It makes it easy to add or remove placement rows and columns, as well as insert dummy devices. Used in conjunction with the cell template, it is the fastest way to achieve correct layout of custom digital standard cells. Although it is particularly well-suited for FinFET-based designs, it is equally as good on planar CMOS nodes.

Generating the devices and placing them such that they meet all the design rules and will produce a robust working design represents about 30% of the layout time. Using a layout assistant like the symbolic editor really speeds up this task and allows layout engineers to boost productivity for the layout task, as well as building a library of topologies for IP reuse.

To learn more about how the symbolic editor can help you to rapidly create custom digital cells, check out Webisode 5 in the Custom Compiler Assistants Webisode Series that shows the symbolic editor in action.

Next time we will take a look at how we can use the symbolic for analog cell design.

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