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Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More »

We’ve Come a Long Way! (Part 2)

 
February 10th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys

If I say ‘sticks’ to you, what comes to mind? Well, you could reply with “bits of wood” or “an American rock band from the 70’s” or “a river in Hades” and you would be correct. However, when you ask the question in the context of EDA, well, that’s a different story.

‘STICKS’ or ‘stick diagrams’ refers to a technology called symbolic layout. My first introduction to symbolic layout was the CALMA STICKS package that emerged around 1983.

STICKS was a netlist-driven symbolic design package that produced correct-by-construction physical layout directly from the logical netlist. Although a great concept, it never really took off. The effort to bring the logical connectivity into the layout by means of a netlist did not deliver a high-enough ROI in the eyes of the layout community.

However, as the layout systems evolved, schematic capture packages began to appear, and once these were accepted as an integral part of the design methodology, it led the way to the next phase of layout automation. Once you had the schematic captured electronically, the next step was to drive the generation of the layout from the schematic device parameters. The introduction of parameterized cells (Pcells) made this possible and Schematic Driven Layout (SDL), as it became known, slowly started to gain acceptance within the layout community. The main reason for acceptance was Pcells. Pcells were, in essence, a computer program that would draw the polygons that made up the physical device and make it into a cell that could then be placed in the layout. If you changed the width or length of a transistor on the schematic, the Pcells would regenerate the cell to match the new parameters. Pcells removed the chance of having a mismatch between the physical device and the logical device. The layout devices were correct-by-construction because they were generated using the exact device parameters that were in the schematic. One Pcell could create any number of different cells, which also helped keep the library of cells needed to create a design much smaller. In addition, there was the added bonus of being able to see the connectivity in a graphical manner through ‘flight lines’ which were drawn between the pins of the devices that were logically connected together. This visual aid made connecting up the devices a lot easier. There was now a tangible ROI that delivered an overall boost in layout productivity.

So, are we done? Is everyone using schematic-driven layout (SDL)?

Well, although it is widely used, not every layout engineer is using it. The issue is that most implementations of SDL require a strict adherence between the logical and physical hierarchy. Whilst this may be good for the logical hierarchy, it may not always be best for the physical implementation. This shortcoming has led to the practice of only using SDL to generate the devices, and then turning it off so that the layout engineer can manipulate the physical hierarchy to get the best layout.

So where does that leave us? Have we exhausted all avenues in our search for layout productivity?

Well, I don’t think so.

But that’s another post.

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