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Posts Tagged ‘verification test cases’

Following the Roadmap to Successful Traceability

Monday, September 23rd, 2013

If DO-254 is both the mission and the map required to achieve compliance, then traceability represents the roads on that map. Consider this.

- Roads connect two or more places on a map; traceability connects two or more elements in a project (such as functions, requirements, concept, design, verification data and test results).

- Road names help identify specific places that are linked to it; traceability names help identify specific project elements that are linked to it.

– In the absence of roads, reaching your destination is practically impossible;  in the absence of traceability achieving compliance is also practically impossible.

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Demystifying Traceability

Monday, June 17th, 2013

For DO-254 Compliant FPGAs and ASICs

I have been getting a lot of questions from our customers about traceability in the context of DO-254 and airborne FPGAs and ASICs.  It seems that there are several new concepts and terminologies associated to traceability that are new to most of us.  So I thought I would shed some light in this blog and explain the basic 5 terminologies. Also I have always liked the word “demystify”, but never had the chance to use it – so here is my chance.

Traceability – Traceability is the activity that maps all of the design and verification elements back to requirements to ensure that what is being built and tested is based on the requirements. Traceability is the correlation between system requirements, FPGA requirements, conceptual design, HDL design, post-layout design, verification test cases, testbench and test results.

Downstream Traceability – A top to bottom reporting activity that shows the mapping or correlation between system requirements, FPGA requirements, HDL design, test case, testbench and test results.  Running a downstream traceability can expose FPGA requirements that are not implemented by any HDL function or not covered by a test case.

Upstream Traceability – A bottom to top reporting activity that shows the mapping or correlation between test results, testbench, test case, HDL design, FPGA requirements and system requirements.  Running an upstream traceability can expose derived FPGA requirements or unused HDL functions.  Tools like Spec-TRACER can also use upstream traceability to expose all of the design and verification elements associated to a FAILED simulation result.

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