Aldec Design and Verification
Louie De Luna
Louie is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. He received his B.S. in Computer Engineering from University of Nevada in 2001. His practical engineering experience includes areas in … More »
Does DO-254/CTS™ Support FPGAs with Serial High-speed I/Os?
November 20th, 2013 by Louie De Luna
As a DO-254 evangelist, I travel quite a bit attending conferences and meeting customers all over the world. One question I occasionally get from engineers is whether Aldec’s mil/aero verification solution, DO-254/CTS™, supports verification of FPGA designs with high speed interfaces (for example ARINC 818, LVDS, DDR3 or PCIe).
Depending where I’m at I’ll tell them, “Oui!” or “Hai!” or simply “You bet it does”. Occasionally I’ll respond, “화장실이 어디 있어요!” in hopes that someone will kindly direct me to the nearest restroom.
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Tags: Aldec, arinc 818, arinc protocol for high bandwidth, aviation, avionics systems, c/c++ api, do-254, do-254/cts, FPGA, fpga designs, in-hardware verification results, low latency, mil/aero verification solution, safety-critical, uncompressed digital video transmission, waveform
Category: DO-254 Compliance