EDACafe: Verilog-AMS & Multi-Level Simulation

Aldec Design and Verification

Dmitry Melnik
Dmitry is a product manager at Aldec responsible for ALINT™ and Riviera-PRO™ product lines. He has over 8 years of digital design and verification experience, including previous roles in corporate and field applications, technical marketing, and software development with R&D divisions of … More »

Verilog-AMS & Multi-Level Simulation

September 16th, 2013 by Dmitry Melnik

It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2), we at Aldec and Tanner EDA have received many inquiries from the field, conducted a number of evaluations, and deployed our analog/mixed-signal (AMS) design flow with our first mutual customers. In this article, I’ll share more the mixed-signal simulation methodology and highlight some of Verilog-AMS use cases that we have seen in the field.

Digital & Analog HDLs

The Verilog and VHDL languages were designed to handle discrete signals, where the number of possible signal values is limited (e.g. 1, 0, X, Z). Whereas Verilog-A was designed to handle continuous-time (analog) signals, that can take any value from a continuous range at any point.

For the rest of this article, visit the Aldec Design and Verification Blog.

Tags: Aldec, analog, co-simulation, digital, hiper simulation a/ms, mixed-level simulation, mixed-signal, mixed-signal design approach, Riviera-PRO, safety-critical, simulation-based verification, tanner eda, transistor-level implementation, verilog-ams simulators, vhdl languages

Category: Functional Verification

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7 Responses to “Verilog-AMS & Multi-Level Simulation”

selva kumar says:

October 15, 2013 at 11:04 pm

how to run a verilog ams in tanner EDA in t-spice.I want a quick rply pls

Reply
- Christina Toole says:
  
  October 16, 2013 at 11:54 am
  
  Tanner’s front end design tools support Verilog-AMS through co-simulation with a supported digital simulator such as Aldec’s Riviera-Pro TE (other simulators are also supported). Co-simulations are typically run either through T-Spice or directly from Tanner’s schematic capture tool, S-Edit. The Tanner toolflow makes simulating mixed-signal designs easy by automatically dividing the design into analog and digital components and invoking both simulators without user intervention. http://www.tannereda.com/ams
  
  Reply
  - selva kumar says:
    
    October 18, 2013 at 2:12 am
    
    Aldec’s Riviera-Pro TE IS A FREE VERSION SIMULATOR ? . TELL ME THE LINK TO DOWNLOAD THAT SIMULATOR AND LIST OUT OTHER SIMULATOR ?
    
    Reply
    - Christina Toole says:
      
      October 23, 2013 at 3:02 pm
      
      Riviera-PRO TE is available as a part of HiPer Simulation A/MS package. Tanner EDA hosts both T-Spice and Riviera-PRO TE, and you can download the package from Tanner’s website at http://www.tannereda.com/support.
      
      Reply
selva says:

October 23, 2013 at 2:42 am

now i get the Aldec’s Riviera-Pro TE how to get license for that. i have already tanner 16 license

Reply
selvakumar says:

October 25, 2013 at 2:57 am

thank you. download that but i want a clear procedure to interface with tanner and how to get license for Riviera-PRO TE.

Reply
- Tanner EDA Marketing says:
  
  October 28, 2013 at 9:37 am
  
  Hi – please contact your Tanner EDA Sales or Support representative for this request. You may email us at sales@tannereda.com or visit our website at http://www.tannereda.com and complete an online request form. We will respond to your request within 24 hours. Thank you.
  
  Reply