Companies have been forced to choose between FPGA and ASIC implementations of integrated circuits. The gulf between FPGAs and ASICs is as great as between the Poppa Bear and the Momma Bear in the story. I won't say which one is the Poppa and which is the Momma.
In relative terms ASIC development entails an enormous amount of non-recurring engineering (NRE) charges, takes a considerable amount of time and engineering talent, requires sophisticated design tools and has a significant amount of risk. There is a technological risk that the targets for performance, reliability, yield and schedule will not be met. With shrinking product lifecycles time to market is crucial to business success. Second and third to market vendors will encounter a smaller remaining available market and have less time in market to mine it. There is also a marketing risk that product requirements may change during the long development process due to shifts in end user preferences or the actions of competitors. The lack of programmability makes it difficult to respond such changing requirements. In a series of studies Collett International Research has shown that first silicon success rate for ASICs has fallen from 48% in 2000 to 39% in 2002 to 34% in 2003. Forty percent of designs required more than one re-spin. Logic and functional flaws had the largest failure contribution rate at 45%. More than 82 percent of these flaws arose from design error in which bugs remained hidden in the design through to tapeout. With shrinking geometries mask costs and fabrication turnaround time have increased dramatically. Due to their high risk and considerable NRE cost the number of ASIC designs has been decreasing dramatically from over 10,000 in 1998 to less than 3,500 in 2002. IC Insights reports 1,400 standard cell designs in 2003.
On the positive side the manufacturing cost per unit volume even when NRE costs are included can be very small for large volume applications such as cell phone and mobile entertainment devices. All standard cell ASICs have relatively high performance and low power consumption.
By contrast FPGAs have little NRE costs and can be developed comparatively quickly with less complex tool sets. Programmability gives flexibility to respond to changing requirements. Taken together this means that the technical and marketing risks are small. Unlike ASICs there is a relatively low minimum order quantity. In fact FPGAs are often used as prototypes for ASICs to minimize risk. On the negative side programmability comes with a cost in terms of silicon overhead. Consequently FPGAs have high unit cost, lower performance and higher power consumption. FPGA vendors are following the technology curve to deliver higher performance at lower cost but the gulf with standard cell ASICS remains.
A third choice is now available, namely Structured ASICs (SA). This split-the-middle choice would be characterized by SA vendors as the “best of both worlds” or as the Baby Bear said “Just right”.
A structured ASIC typically consists of predefined logic cells and configurable memory cells in the form of an array. Each of the cells contains customizable combinatorial logic to form adders, multipliers, multiplexers, flip-flops and so forth. The mask layers required to build the logic-cell array are common to all customer designs. The logic cells are then customized and interconnected with a few metal layers on top. The SA has built in clock domains, preconfigured DFT circuits (scan, BIST), power distribution, embedded IP and so forth. This simplifies and reduces the design effort.
A structured ASIC is designed and fabricated by the vendor with the last few metal layers left undefined. The customer makes the final connections to produce a custom IC. The prefabricated wafer, also known as a master slice, is generally produced in volume and stockpiled for future customer use. This approach shares the device's development cost across multiple customers. The customers provide designs in RTL or netlist form to be mapped onto the cells. The wafer is retrieved and the upper metal layers used to implement the design.
Structured ASIC vendors really provide a service that delivers the customer's design. This generally involves third part fabrication and manufacturing (packaging, testing). The design tools used are a combination of proprietary and industry standard EDA tools.
Structured ASICs offer the performance, power consumption and unit costs associated with standard cell ASICs along with the low NRE and fast turnaround time of an FPGA. The table bellows is a qualitative comparison of the three approaches.
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Most SA vendors publish a graph of total cost versus volume comparing their specific SA solution to FPGA and standard cell. Figure 1 represents a qualitative comparison with a generic SA solution. The Total cost includes engineering cost, mask NRE and manufacturing cost (volume*unit cost). Region A is the sweet spot for FPGA, region B for structured ASICs and region C for stand cell ASIC. The dividing lines are not absolute. If the volume forecast increases, a firm can choose to continue to use the existing design and corresponding fabrication process or move up to the next level depending on their confidence in the revised forecast and the size of the anticipated jump in units. It is possible that a particular product may pass through all three regions during its lifetime.
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Several people I interviewed for this article have said that structured ASIC is still a missionary or evangelistic market. Much needs to be done by the vendors to plant the seed, educate designers and their management about the benefits of this solution. Towards this end Chip Express, Lightspeed, Synplicity, and Tera Systems announced just this past February that they have formed the “Structured ASIC Association” (SAA). The founding members are collaborating to firmly establish Structured ASICs as a unique market segment and educate the industry about this new technology. Launched by the SAA, the new Structured ASIC website ( http://www.structuredasic.com) was developed to provide a comprehensive source of information about Structured ASIC technology. The SAA defines a Structured ASIC as “an integrated circuit architecture that delivers reduced entry cost and faster time to silicon using a predefined arrangement of late-stage mask-customizable logic and pre-diffused macros.” This means customers can expect low NRE, low unit pricing, and fast turnaround time for prototype and production Structured ASIC devices.
In the press release announcing its formation the SAA claims that customers using Structured ASICs reap many of the performance and cost advantages of a full custom ASIC in a device which can be fabricated in as little as three weeks. Using this revolutionary new technology, design teams can build complex ASICs for 25 percent or less of the development cost of a standard cell device, at a unit cost approximately 90 percent less than a complex FPGA.
High-tech market research firm In-Stat/MDR forecasts that Structured ASIC product revenue will grow from $5.2 million in 2002 to $460 million in 2007, a compound annual growth rate of 145%. Communications application such as networking infrastructure and cellular basestations will account for more than half the consumption. The next largest end-use category will be EDP, particular storage. The Americas will dominate product consumption, accounting for more than one-half of all product dollars but other regions will grow more rapidly. Another analyst firm iSuppli has said the structured ASIC market will grow to reach $250 million in revenue by 2007. The group said sales reached $70 million in 2003.
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Structured ASIC Vendors
The following paragraphs describe the approaches that a few representative firms have taken for structured ASIC.
San-Jose based and privately held eASIC Corp. was founded in 1999 by Zvi Or-Bach, the founder of Chip Express. The company has a head count of more than 40 people including an R&D team located in Romania. I spoke with Larry Cook, VP Technical Marketing. Among other things he sees Structured ASICs as a vehicle for small startup companies to introduce new niche products which may become tomorrow's killer applications.
The patented eASIC architecture is an array (FelxASIC) of logic cells (eCells) with SRAM based LUTs and flip-flops, built with bulk silicon and a few lower metal layers. The eCells are connected to a segmented wiring grid built with upper metal layers that can be customized with a single VIA mask to implement a specific design. Logic functionality of the eCell is achieved by downloading a bit-stream to configure the LUTs and flip-flops after powering up the device, very similar to an FPGA. Since logic customization is achieved in this manner there is no need to have a connection go all the way from the upper metal layers to the substrate for programming as is the case with FPGAs and other structured ASICs. eASIC's higher density coarse grained cells, allow multiple levels of logic in a single cell, resulting in fewer, shorter wires connected with low resistance vias, achieving power and performance that is close to standard cell. Since only one VIA layer mask needs to be customized, it can be achieved by direct-write eBEam, making it possible to deliver a zero NRE ASIC. In general the amount of data to be written for a VIA layer is much smaller compared to that of a metal layer (1% of the area vs. 30%) . eASIC's fabric yields about 10 times higher throughput from Direct-write e-Beam machines, compared to metal customization. This makes direct-write eBeam a practical and cost effective alternative to lithography for prototyping and low volume eASICs. Using Direct-Write eBeam eliminates the customization tooling cost, shortens time to market and adds manufacturing flexibility. Further, multiple projects even from different customers can be produced on the same wafer which can reduce minimum order quantities. Testing the chip and debugging a design is facilitated because different bit patterns can be downloaded to the chip to test isolated sections of the design.
Since the logic is constructed of SRAM, any logic area can also be a high density dual port SRAM. Structured eASIC arrays contain a minimum amount of Block Memory, and when additional memory is required, the logic cells can be configured as memory. The eASIC fabric includes pre-built custom address decoders, so the memory constructed from that fabric has the performance of custom memory. Interchanging logic and memory on the eASIC array, achieved at an efficient conversion rate, provides designers with the flexibility to accommodate wide varying memory requirements for different designs without the need to move to a bigger array. Other structured ASIC vendors offer less flexible solutions with fixed maximum memory bits and fixed maximum logic gates.
The standard eASIC methodology matches the conventional ASIC design flow. It uses Synopsys synthesis tools, Cadence place and route tools and SynTest for APTG. Proprietary eASIC tools for place, route and mapper are also available.
The FlexASIC family is fabricated by ST Microelectronics in 0.13µ CMOS process technology, back-end manufacturing (packaging, testing) is provided by Flextronics. The product family runs from .6 to 3 M usable ASIC gates and 400k to 1,500 k bits bRAM with typical system speed of 250 MHz.
On April 27th eASIC announced that as the next phase in its business strategy of fabless semiconductor model it will offer Structured ASIC chips, while continuing to provide Structured ASIC technology as licensable IP core for embedding in System-on-Chip. A Structured ASIC chip is being developed in partnership with Flextronics Semiconductor. This Structured ASIC product family will be fabricated by a world-class IDM semiconductor company, at 0.13 micron, and is scheduled for production launch in early Q1 2005.
In 1985, ChipX, formerly ChipExpress, was formed as an activity within the Israeli high-tech holding company, Elron Electronic Industries, Ltd. Starting in 1989 as a prototyping service company, ChipX emerged in 1995 as a complete ASIC solutions provider.
Since 1999 ChipX has been moving away from its original business of providing quick-turnaround prototyping for ASICs, as the market became dominated by FPGAs. The firm now has revenues only from its structured ASIC products.
ChipX is a privately held company that has raised approximately $56 million in capital financing. The most recent round of $12 million in March was accompanied by the name change. Semiconductor foundry UMC is among the investors. Current headcount is around 110.
ChipX has completed over 1,000 Structured ASIC designs and has shipped millions of devices. I spoke with Elie Massabbki, VP of Marketing, who joined ChipX in late April. He said he has been pleasantly surprise with the business potential of structured ASICs from Mindspeed Technologies. He sees continued growth in the short terms and forecast SA will be just as big as FPGA in the 2009/1010 timeframe. Mostly this will be craved out of ASIC market with some from the FPGA market.
ChipX customer base is 30% military and aerospace, 25% communications and 24% industrial and instrumentation (medical, automotive, office automation) and the rest data processing (storage, computing, and printing). CHipX has a design service specifically targeting military customers with Military Reliability Screening (Mil Std. 883B), Military Assembly (Mil Std. 883B), military screening flexibility and extensive packaging portfolio. ChipX also offers conversion of legacy designs to advanced process technology and migration of 5V designs to 0.35µm technology.
The ChipX product line contains four families of structured ASICs. The 0.25 m product line provides exceptional gate density, 2.5V operation and high-speed serial I/O capability. The 0.35 m product line represents a cost-effective process for mainstream 3.3V ASIC production. The 0.6 m product line is low cost and targeted at industrial and military customers with its radiation resistance and reliability.
For prototyping ChipX offers 5 days from sign-off to prototype delivery. For production fab, test and assembly turnaround of 5 days low volume, 3 weeks mid volume and 5 week high volume. Flexible minimum order volume and fast production amp. Extensive packaging library, Fast-turn prototype packages, Hermetic and military packages.
Altera Corporation founded in 1983 is the pioneer of system-on-a-programmable-chip (SOPC) solutions. In 2003 the firm had revenues of $827 million. Today the installed based numbers 20,000 customers and the employee headcount is about 2,000. Altera offers device families in the area of CPLDs, low cost FPGAs, high-density FPGAs and structured ASICS. In its most recent quarter FPGA sales accounted for 66% of total sales, CPLD sales accounted for 26%. Altera is number 2 behind Xilinx in the FPGA market. I spoke with Peter Wu, the Director of Product Marketing for Hardcopy the company's structured ASIC product line.
First I asked about the name “Hardcopy”. He said that the term come from the process of hardening an FPGA design into a device. Given Altera's strength in the FPGA market I asked how they were positioning their structured ASIC offering, Harcopy. He admitted that their sales force had some misgivings when the product was initially presented as a cost reduction approach for FPGA customers. Today Altera is saying if a customer can design and ship in FPGA, they should do so. The real opportunity for SAs is the ASIC market. For customers interested in SAs Altera is recommending a design flow in which a FPGA is actually produced for early demos, customer trails, beta test and so forth It is only a matter of a few weeks to migrate to SA since The SA is drop-in, pin compatible replacement.
This way a designer can fully verify in silicon at effective speeds rather than rely on simulation. The process of migrating from FPGA is seamless. One starts with the programming files and the constraints from the FPGA. For those using FPGA based design there is no change in design flow or tools (Quartus II). For ASIC designers one can used Synopsys DC FPGA announced in March.
Altera's mask-programmed HardCopy device base arrays are developed from their equivalent FPGAs by removing the configuration circuitry, programmable routing, and programmability for logic and memory. The silicon development methodology results in die size reduction of about 70% compared to the equivalent FPGA and provides considerable performance and power consumption improvements over the FPGA. This process maintains the FPGA architecture allowing the same FPGA-proven netlist to be seamlessly migrated to a HardCopy device with minimal risk.
Altera generates a Verilog structural netlist from the functionally proven FPGA design file and checks the design to make sure it adheres to industry-standard DFT rules. Altera creates an optimized layout of the design using the placement and timing constraints provided in the deliverables and verifies the design to satisfy timing requirements. The design's migration and verification is complete within three weeks. It is sent to the foundry for prototype manufacturing. Prototypes are available within five weeks. Volume production commences once the customer has approved the prototypes for satisfactory functionality and devices are ready for shipment in eight weeks. The total time for customers to obtain production devices in approximately 18 weeks.
There are no risks associated with the migration process because the FPGAs are rigorously tested, mass-produced, and shipped in volume before their equivalent HardCopy devices are fabricated, thus maximizing first-time success and meeting customers' time-to-market demands.
NEC Electronics America formerly NEC Electronics, Inc, was established in 1981 as a wholly owned subsidiary of NEC Electronics Corporation. The company is a developer, manufacturer and supplier of semiconductor-based advanced technology solutions, system solutions and platform solutions backed by local technical support and the global manufacturing capabilities of its parent company. I spoke with Steven Kawamoto, Senior Marketing Manager.
Steven said that ISSP market is 50% communications, 25% industrial and instrumentation, and 25% storage and computing. He claims 30 tape outs using ISSP1. NEC does all the wafer fabrication, packaging and testing. They have facilities world wide including at Roseville, CA.
NEC's structured ASIC product line is called ISSP for Instant Silicon Solutions Platform. Each NEC Electronics' ISSP design begins with a prefabricated master made up of an array of complex multi-gates, embedded IP cores, built-in test circuits, clock domains and power lines. The upper metal layers are easily and quickly placed, routed and fabricated to satisfy the unique requirements of each individual design. ISSP-based products consume much less power than a comparable FPGA and also have lower NRE costs than cell-based ASIC devices. There are three product families: ISSP1-standard, ISSP1 high-speed and ISSP2.
Devices in the first-generation ISSP1-STD family have embedded high-density SRAM, analog phase-locked loops (APLLs) and delay-locked loops (DLLs). Based on NEC Electronics' production-proven UX4 CMOS process with five metal-layer (aluminum) technology, ISSP1-STD devices feature advanced 0.13 µm (drawn) transistors, system clock speeds up to 250 MHz, and a core voltage of 1.5V that results in low power dissipation. NRE costs for the ISSP1 products should be below $100,000.
At the heart of the High-Speed Interface family is NEC Electronics' high-performance SerDes core that supports frequencies up to 3.125 Gbps and serves as the key component between the ISSP architecture and various industry-standard high-speed interfaces.
Based on 90-nm UX6 technology, ISSP2 is NEC Electronics' next generation of structured ASIC devices. This platform provides up to 4 million usable ASIC gates, 10 Mb of embedded configurable memory and performance up to 500 MHz. The ISSP90 device architecture is a five to seven metal-layer design with two easily customizable layers to meet individual design requirements.
The EDA tool suite, part of NEC's OpenCad Design environment, includes familiar best in class tools like Teraform (RDC) RT checker, Synplicity Synthesis and Synopsys Design Compiler. If NEC does the routing, they use Cadence Encounter plus some proprietary tools.
On May 24th NEC and Synplicity announced OEM agreement whereby NEC Electronics will bundle and distribute a license for Synplicity's Amplify ISSP Physical Optimizer software within NEC Electronics' OpenCAD design environment for use in the development of its ISSP structured ASICs. The Amplify ISSP physical synthesis software is the result of nearly two years of joint development between the two companies to provide their mutual customers with a unique physical synthesis solution customized for NEC Electronics' ISSP-1 (150nm) and ISSP-90 (90nm) structured ASICs.
Weekly Highlights
Paragon Announces Integration of Nassda HSIM with Paragon's IC Design Platform
Synopsys Presents 4th Annual Tenzing Norgay Interoperability Award to Novas Software
Toshiba to Start Production of Industry's First SoC With the X Architecture
Denali Joins Synopsys SystemVerilog Catalyst Program
TSMC and Synopsys Address Design Challenges for 90 Nanometer and Below with TSMC Reference Flow 5.0
VaST Founder and CEO, Graham Hellestrand, Elected IEEE Fellow
Mentor Graphics Acquires Atair Compiler Technology
Altera Collaborates With Synopsys on Hardcopy Structured ASICs
Atrenta Appoints John F. Rizzo as Vice President of Marketing and Customer Service
Atrenta Raises $11M in Series C Funding; Investcorp Leads Financing to Provide Funds for Accelerated Growth
CoWare SPW Supports VHDL Users with Integration of Mentor Graphics' ModelSim Simulator; Capability Broadens Adoption of SPW as Leading DSP Application Design Solution
0-In Announces SystemVerilog and VHDL Products; Market-leading Archer Verification System Provides Open Standards Support with Availability of SystemVerilog and VHDL Products
TSMC and Cadence Tackle Low Power Challenges at 90 Nanometers and below with New TSMC Reference Flow
Synopsys Delivers Industry-First Comprehensive Low-Power Solution 2X Power Reduction
EVE, Novas Collaborate on Optimized SoC Verification & Debug Flow; ZeBu, Novas Debug Platform Interoperability Reduces Tool Complexity, Learning Curves
Protel autorouter updated
Pulsic Announces Expansion in the U.S.
Avertec and Dolphin Integration announce partnership in Design Check Innovation
TSMC and Apache Address Dynamic Power Closure for Nanometer Design
Pulsic Announces New Lyric Analog Product for Dedicated Analog/Analog RF Design
Apaches' SkyHawk Removes Guesswork from Power Grid Design in Nanometer Chips
Cadence Announces First Encounter Global Physical Synthesis; New Second-Generation Physical Synthesis Breaks Capacity and Speed Barrier, Supports Very Large-Scale SoC Design
Cadence and ASML Sign Multi-Year Business Agreement to Develop Advanced DFM Solutions; Collaboration Links Best-of-Breed Design and Lithography Solutions
Mentor Graphics Enters Into Agreement to Acquire 0-In Design Automation
Celoxica Achieves Automation for SystemC Synthesis; Advanced Synthesis Technology Bridges the Design Flow Gap to Generate High Productivity Implementation Path From SystemC
Synopsys Reduces AMBA Bus-Based SoC Design Time With DesignWare Library
Synopsys' coreAssembler Tool Decreases Design Time for Leading Semiconductor Companies by Up to 67 Percent and Significantly Reduces SoC Cost
TSMC Selects Atrenta as Reference Flow 5.0 Partner for Power Closure and IC Integration Flows
More EDA in the News and More IP & SoC News
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