>> VHDL Discussion Board
Thread views: 10094 View all threadsNext thread*Threaded Mode

(Stranger )
02/23/07 12:06 AM
Cadence Report this article as Inappropriate to us !!!Login to Reply

1.can anyone give me the whole flow of pks_shell cadence tool .I am writing a vhdl file and I can go upto the" build generic" and optimize(giving error: floorplan area not specified)and write it into a verilog netlist file.if i give this verilog netlist file as input to the encounter ,it is giving error in the verilog file.

2.Does encounter tool takes input of netlist in verilog format only or a vhdl netlist can be given to it .....?

Jump to


Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise