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(Stranger )
02/10/10 08:44 AM
Draw timing diagrams from VHDL,Verilog, and VCD Report this article as Inappropriate to us !!!Login to Reply

Hi All,

Build timing diagrams directly from simulations using VHDL, Verilog,  or VCD files.

The latest version of the TimingAnalyzer reads VCD files and converts it to a timing diagram, then saves it as a timing diagram automatically.



Dan Fabrizio


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