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Rahul
(Unregistered)
01/28/06 09:06 AM
Logic path delay for mux with enable line Report this article as Inappropriate to us !!!Login to Reply

Hi,
I have a basic doubt regarding the timing calculation for a multiplexer with an enable input. The mux is a part of the combinational logic path between a set of input and output registers.
I need to find the maximum logic delay in this path in order to compute the max clock frequency, as well as any hold time violations.
How are the mux 'delay from data' or 'delay from enable' to be used for finding the logic path delay?




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