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| Clock Domain Crossing (CDC) Design Techniques | In today’s era of complex SoCs various design sub-blocks running at different
frequency are common occurrence. Even with today’s advance functional verification solutions, CDC signals pose unique and challenging issues. While STA is an integral part of the timing closure solutions, it does not address the issue of proper CDC implementation. To say the least, CDC issues if not detected in late design stages or worst during post-silicon validation can lead to heavy financial penalties.
Various issues caused by CDC can be bracketed into two basic problems,
1. Issue of meta-stability propagation.
2. Functional issues due to signal crossing clock domains.
The following article describes design methods to avoid the above two problems. |
1743 |
| FPGA Floorplanning | Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them in such a manner as to meet the sometimes conflicting goals of available space (cost of the chip), required performance, and the desire to have everything close to everything else. |
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Total 2 links listed (include in sub-categories).
