The southeast of France may have changed a bit since the early part of the First Millennium when the city of Grenoble sported the name Gratianopolis in honor of the Roman emperor Gratian. Since that time, the region’s been Burgundian, Carolingian, Austrian and French. Today, it’s home to an extensive technology community, several major universities specializing in science, engineering, and management, a lot of Olympic-caliber skiing, and a téléphérique. One thing hasn’t changed, however. It’s still cold in December.

If my Vista desktop gadget can be believed, at this writing it’s 0 degrees Celsius in Grenoble. Given that fact, why would anyone in their right mind leave balmy Northern California, as I’m about to do, and travel for hours and hours to reach such a remote and chilly city at the foot of the Alps? The answer is simple: The Design & Reuse Center is in Grenoble and every December hundreds of people converge there to celebrate All Things IP.

For 16 years in a row, the D&R IP Conference and Exhibition has been a lynchpin in the annual rhythm of meetings and confabs that define the IP industry. This year’s conference takes place on December 5th and 6th, and for the first time I will be there. I’m moderating a panel on the 6th that includes a keynote from OneSpin Founder and CTO Wolfram Büttner, and an hour-long discussion with Infineon’s Steve Neill, STMicro’s Olivier Haller, Certess’ Mark Hampton, and Cadence’s Eric Panu. Hopefully, these gentlemen will have good news for our audience as they answer the question: “Highest Quality IP: Dream or Reality?”

Of course, there are plenty of other events and keynotes taking place during the 2-day IP07 conference, not the least being a panel on December 5th moderated by IPextreme CEO Warren Savage. Warren’s panel will include Mentor Graphic’s Bill Martin, Improv Systems’ Victor Berman, OCP-IP’s Ian Mackintosh, and Synopsys/SPIRIT’s Pierre Bricaud. These gentlemen will be asking: “Who Should be the Standards Torch Bearer for IP?” Given recent developments with VSIA and IEEE, this panel promises to be among the most interesting of the conference.

I had a chance recently to speak by phone with Warren Savage about his upcoming panel, as well as many of the concepts (and mis-concepts) related to IP. I learned quite a bit during the call and expect to learn even more in attending the panel.

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Warren Savage & The Golden Age of IP

The way Warren Savage tells it, we’re on the eve of The Golden Age of IP and he’s probably in a position to know. Savage’s company, IPextreme, specializes in helping customers bring their internally developed IP to market.

Warren was sitting in his offices in Campbell, California, when we spoke. He told me his business is doing exceptionally well, plus he explained how he got into this particular niche in the first place: “I’ve been in the IP business for a long time. In fact, I helped start the DesignWare business unit at Synopsys in the mid-1990’s. When I left Synopsys, I was inspired to start IPextreme because I saw a need in the industry for the services we provide. The company has just come off of a record quarter, which is a great way to be celebrating our 4th anniversary in January 2008.

“IPextreme is like a record label for semiconductor companies. We work with the engineering groups within our customer organizations to help them produce IP in a format that can be licensed outside of the company. Customers like Freescale and Infineon work with us to identify their key IP assets, and then we serve as their exclusive licensing agent. From a legal standpoint, most of the licensing is done using a standardized form that we’ve developed over many years of working with IP. It’s a reasonable and standardized license that pretty much all of our customers are very comfortable with.”

Savage declined to give further details regarding his business relationship with his customers: “We consider the format and wording of our licenses, in conjunction with our business model, to be our crown jewels. So of course, we don’t expose it to the media. Suffice it to say that only our partners know the details and the financial arrangements included in the model.

“It’s truly our secret sauce,” he added with a chuckle.

Propriety details notwithstanding, Warren and I launched into a lengthy Q&A about the current state of affairs in the IP industry.

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Q – If IP is the wave of the future, why hasn't it caught on as vigorously as one would intuitively expect it to?

Warren Savage – That anyone would even ask such a question is intriguing, because today IP is a fundamental part of the way the semiconductor industry works. This year alone, IP will be a $1.5 billion industry, quickly approaching 50 percent of the entire EDA market. Yet, the IP industry is less than half as old as EDA. In fact, 60-to-70 percent of the customers we deal with use some kind of third-party or internally developed IP. Add to that, the fact that the number of customer designs is shrinking – we’ll be down to single-digit growth in new designs within 10 years, or even 5 according to some – and it’s clear that the industry stands on the verge of The Golden Age of IP.

Q – So if the use of IP has actually caught on as a widespread, standard practice, who doesn’t have the eyes to see that this is the case today?

Warren Savage – We’ve definitely got some problems on the journalistic side of things. When I got involved in IP in the mid-1990’s, IP was really a hot industry. Those were the dot-com days and everybody was getting wrapped up in an irrational exuberance about IP. A lot of bad companies came online as a result, and most died in the first part of this decade along with the recession in high tech. Meanwhile, that same recession caused a huge drop in design starts, which in turn created a lot of pressure on companies to be much more careful in [their investment practices].

So many companies going out of business 5 or 6 years ago sent a message to the journalists that IP is dead. In reality, we saw it as a consolidation within the industry, not the death of the industry itself. For instance, when I was at Synopsys we bought various IP companies, while others were snapping up IP companies as well. That was tough for the media to understand at the time and they still may not understand, particularly because you can’t touch, hear, see, or feel IP. I refer to IP as the Dark Matter of the Semiconductor Universe. It’s big, it’s present, and it’s mostly invisible. [Savage chuckled]

Q – Is the fact that IP is invisible an advantage to users?

Warren Savage – Absolutely. We find a lot of the time that IP users don’t really want to talk about what IP they’re buying. They want to keep that information under wraps, because they don’t want other people to know what technology they’re incorporating into their chips.

But also – IP is boring and it’s old news, which is another reason why it may not get extraordinary amounts of journalistic attention. For instance, that a company licensed some IP two years ago for a chip they’re announcing today is not news. That time lag between when the IP licensing deal was signed and the customer’s willingness to talk about it [makes for a somewhat boring story in the press].

Q – So is the IP stale by the time the chip it‘s sitting in reaches the market?

Warren Savage – No, it’s not stale, but the story is still boring. There are certain staples that you have to have on a chip – memories, standard interfaces, etc. The IP that’s on a chip is not really big, shockingly new technology. It’s mostly very meat-and-potatoes type of stuff.

Q – Okay, so what‘s the IP business model? Product or Services? And, why am I still able to ask that question today?

Warren Savage – Today, we believe with certainty that the IP business model is a product model. You can look at many of the “IP” companies that died in the downturn and you’ll see that they were really services companies masquerading as IP companies. On the other hand, companies like ARM, MIPS, Synopsys, and Rambus are real IP companies that are product companies. For those people, services does not factor into the delivery of the product.

Q – But even for the companies you mentioned, isn’t there still a services aspect to their business offerings?

Warren Savage – Yes, certain companies will add a service component as an adjacent aspect to their business, for instance helping customers move from one technology node to another. But more typically, the IP is licensed as a product, even if some vendors come in and offer services to their customers [to help integrate that IP].

Q – So the services aspect of an IP company is not so much a comment on the business model as it is a comment on the shelf life of a design?

Warren Savage – Yes, that’s an accurate statement.

Q – If the IP business model is a product model, why do people still doubt the product? And why is there still so much hand holding (a.k.a., “services) involved between the IP vendor and the IP customer?

Warren Savage – It’s still a product!

I can’t really talk about my experience at Synopsys, but I did run the entire DesignWare engineering group there, which consisted of a hugely diverse population with thousands of products and hundreds of customers. The fact is, we supported those customers with a very small team. The products were highly packaged and the customers used [them] with ease. That a services component crept in was only a legacy of those companies that Synopsys had acquired that were really services companies in the first place, and not really IP companies.

People have been right to be concerned about the quality of IP because they’re taking on an enormous risk in banking their product success on third-party IP. When you buy IP, you’re taking an enormous gamble that the vendor will stand behind the product.

Q – That’s actually a point that came up during the panel that I moderated this past June at DAC. I had Mike Muller from ARM, Gabriele Saucier from the Design & Reuse Center, and Paul Bromley from STMicro on the panel. Mike Muller insisted that IP customers should only go with big, established IP vendors, yet Madame Saucier has over 400 partner companies in D&R, so Muller had to explain how there can be so many IP vendors if only the big ones deserve to succeed.

Warren Savage – [chuckling] Yes, the Big IP Companies have been trying to squeeze out the Little Guys in IP with that “Big Guys Only” argument for some time. However, there actually is a legitimate argument that says customers should only deal with proven IP from proven IP vendors. Again, it’s our secret sauce that all of the IP we provide to our customers has been wrung out at the big IDMs, which supports Mike Muller‘s argument to a certain extent.

And yes, I also think that customers are right to be cautious about buying from IP vendors who are not big, established providers. We oftentimes sell products with the explanation that buying from big vendors like Synopsys and ARM makes sense. Of course, there can be some differentiating IP purchased from the smaller vendors, but [caution should be the name of the game] for customers in that case.

Q – When will we have an independent entity that benchmarks IP, or is that simply never going to happen? If it's not going to happen, please name the 3 top reasons why not.

Warren Savage – That’s actually a crazy question, because I don’t see that such an entity will ever be needed. I don’t see any such thing ever existing, even for analog IP.

For instance, there’s no benchmark company for EDA tools. In fact, if you’ve ever bought EDA tools from the vendors, they actually prohibit you from benchmarking their products. That prohibition is common and is written into the sales contracts and agreements. You can benchmark the tools for internal knowledge, of course, but you can’t publish the results.

Q – How long has that been the case?

Warren Savage – We were doing it that way when back when I was at Synopsys – it’s been the case for a long time. [Similarly], we will never see an entity for benchmarking IP in the industry.

Q – What about something like EEMBC that benchmarks microprocessors?

Warren Savage – Yeah, those guys do provide that service, but even that example is controversial. We routinely see those benchmarks arranged for marketing purposes only. Benchmarking IT tools, for instance, may provide some useful information, but I don’t see the need for it in IP. So, the 3 reasons you’re not going to see an industry body that benchmarks IP:

1) It’s not needed and there’s no precedent.

2) If you look at some of the IP we have in our portfolio which includes 40-some titles, the IP Universe is so vast – as you said, there are over 400 companies in Design & Reuse – and the IP is coming in so fast and changing so fast, it’s just not possible to do meaningful comparisons. It’s just too rich a stew.

3) Who’s going to pay for that benchmarking? There’s no tax I could pass onto any customer that would pay for it. Even a year ago when I talked to the folks at VISA, it wasn’t clear who could do this.

Q – Speaking of that, what happened with VSIA?

Warren Savage – They actually got off to a horrible, rocky start. I’m moderating a panel at the IP07 show in Grenoble, where I hope to have some additional conversation about [these kinds of changes in the industry].

Q – There are lots of adjacent business opportunities around IP, not the least being vetting IP and aggregating IP across firewalls and time zones. Are these businesses the real opportunity in IP, versus the more “traditional” IP provider business model?

Warren Savage – I disagree with your questions because I wouldn’t consider IPextreme, for instance, to be an adjacent business to IP. We have a unique model about where we get our IP. We compete against ARM and Tensilica on the processor side, and Boshe on the automotive side, so clearly we have real competitors that we going up against.

Plus, I consider that most of my engineering staff lives at companies like Freescale and Infineon, because they’re the actual developers of the IP. They’re developing IP primarily for internal products, but are also getting an additional life and market for their IP through our external channel.

Q – Do you help lead your customers through the documentation effort?

Warren Savage – In the early stages, we had to do a lot of heavy lifting with our customers to convert what they had into something more commercially viable. But as we have matured, both for internal purpose and for commercialization, the developers have been getting better at generating documentation so that it can go into our channel more easily. New IP being generated today for internal purposes is much closer to what the commercial sector really wants now. It’s pretty intriguing to observe.

Q – Do you charge your customers for leading them through the documentation effort?

Warren Savage – Yes, we do to charge them for that.

Q – Can you talk about innovation in the IP industry – in particular, differentiate between innovation in products, innovation in IP aggregation, and innovation in other sectors. This question falls out of a comment from a recent conversation I had with eSilicon’s Jack Harding about what really constitutes innovation.

Warren Savage – I agree, eSilicon does a great job on the innovation side, but on my side I tend to look at the markets at a higher level. I’m very bullish on the future of semiconductors, in particular IP. We really are entering The Golden Age of IP!

IP is becoming so pervasive in the ways engineers think about their chips – there’s a shift to a whole new level of thinking. For instance, if you look at the iPhone, the semiconductor IP is sitting 4 or 5 levels away from final product, which allows companies like Marvel, Samsung, and Apple to innovate at a much fast level than ever in the past. I think if you’re working at one of these large semiconductor companies, you’re putting together some very interesting [products using IP].

Q – If products are built on standard platforms, how do we differentiate?

Warren Savage – That’s a good question, but only if everything is static and there’s only one finish line. However, we’re seeing the finish line moving every day.

What used to be an IP block yesterday, is just a part of a chip today. What was a whole chip, now is a whole sub-system, which is part of a much bigger system. Five years from now, it will be an even bigger platform. The chip itself is turning into IP, which is included in a bigger chip with no end in site.

One of the things we license – the ColdFire technology from Freescale – is licensed in two different forms: the ColdFire CPU core, which is just like an ARM core product, and the ColdFire Standard processor platform, which is a whole set of stuff, as well as a rich set of software that’s available for licensing, sometime as freeware. Customers can drop a whole Voice-over-IP platform into a design, including all of the software, this way and can leverage a whole bunch of legacy IP [in the process]. What used to be a [stand-alone] chip at Freescale, is now a super module.

Q – Isn’t it just staggering, the scale of these things?

Warren Savage – Yes, we can have half a million gates as a block of IP. It used to be that a half million gates was a whole chip, now it’s just a corner of a chip.

Q – How does a customer figure out what IP might be available for a pending project? Through in-house data mining, through externally available catalogs, or through word of mouth from other satisfied customers?

Warren Savage – From what we hear, the Number One source of information is the existing supplier. If an IP company’s doing a good job, almost certainly the customer will come back. Plus there’s always safety working with an established provider. However, everybody also uses Chip Estimate, Design & Reuse, and Google – plus more and more new media.

Because of that, the trade shows are dying. In fact, for us they’ve probably been the worst ROI for finding new customers. So, we’ve really cut back on our show presence – but haven’t really seen any impact on our revenue.

We’re also trying new things. Last year, for instance, we did a private show in Japan and we’re doing another one next month in Taiwan. IP is still very new there, although it’s accelerating quickly. The last time I was in Taiwan, for instance, was in 2003. I went back recently, I was shocked to see how much growth there has been in 4 years. It’s like Silicon Valley there – they know they have to compete against Broadcom and Marvel, so they’re using lots of IP right now.

Our events in Asia are by invitation only. We basically identify good potential customers and invite them to a full day of learning about IPextreme. We also invite in some of our large partners to talk about the IPextreme story with Freescale, Infineon, and other larger multi-billion dollar IDMs. In companies like the ones we’re meeting with in Japan and Taiwan, they find it fascinating to see what’s going on in the U.S. and Europe in this area.

Q – How else does an IP supplier get the word out to potential customers?

Warren Savage – Well, for starters, our blog is working quite well for us. Plus, we’ll be doing some videos related to our business in the next year or so. We constantly have to find new ways to reach people.

Q – Is the traditional press too prejudiced against IP?

Warren Savage – Perhaps some in the press are prejudiced against the industry. But, from the point of view of efficiencies, both in cost and power, there are huge opportunities in IP. We really are at the beginning of the Golden Age of IP.

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[Editor’s Note: Prior to founding IPextreme, Warren Savage created and ran the Star IP Program at Synopsys, and also headed up the company’s DesignWare engineering organization. Previously, he worked at Tandem Computers and Fairchild Semiconductor. Savage has a BS in Computer Engineering from Santa Clara University and an MBA from Pepperdine.]

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Conference news …

* The International Conference on Computer Aided Design (ICCAD) announced increased Asian participation, with particular emphasis on Taiwan, and a first-time non-U.S. contest winner of the CADatholon student design contest held in conjunction with November, San Jose-based conference each year. Per the Press Release: “In addition to the CADatholon Contest, ICCAD 2007 accepted 16 Taiwanese papers this year, which ranks second world-wide. The National Taiwan University alone produced nine of these papers including two of the nine best-paper candidates, as well as one Professor Margarida Jacome Travel Grant – a first for any single institution at ICCAD.”

Sani Nassif, ICCAD Technical Program Chair and 2008 General Chair, is quoted: "There is a lot of leading edge research happening today in other countries, particularly in Asia. ICCAD has always been recognized as the place to learn about the most in-depth, academic work in EDA and in keeping with this tradition we were pleased to offer a range of speakers including those from abroad. The increasingly global set of attendees and flavor of ICCAD is but a preview of what is to come in future editions. Stay tuned for a number of new global initiates in our next conference."

* SAME 2007 Forum, which took place in early October in Southern France, announced 950 visitors, 46 exhibitors, and 23 sponsors. Awards at the conference including Best Paper, Best Start-up, and Best Poster and can be seen on the conference website.

* DATE ‘08 announced 839 paper submissions for the March 2008 conference in Munich, principally in the areas of Design Methods, Applications Design, Test Methods, and Embedded Systems Software. Per conference organizers: “Embedded Systems Software has recently emerged as a highly significant element of the DATE mix as closer ties have been formed between DATE and both the aerospace and aeronautics and automotive systems design communities.”

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People …

* The Silicon Valley Leadership Group announced that Dr. Aart de Geus, Chairman & CEO of Synopsys, has been named recipient of the Spirit of Silicon Valley Lifetime Achievement Award. For a heart-warming testimonial in honor of the award, please visit “Aart de Geus: Renaissance Man”

* Arasan Chip Systems and Chip Estimate Corp. announced that Arasan has joined the Chip Estimate Prime IP Partner Program. Per the Press Release: “As a Prime IP Partner, Arasan is enabling centralized access to information about the company’s IP cores for the electronic design community.”

* Avnet ASIC Israel (AAI) and Elliptic announced a joint effort the companies say will “bring Elliptic's portfolio of security solutions to market in Israel. AAI is a premier provider of ASIC, structured ASIC, COT, and FPGA design services.”

* Cadence Design Systems announced the opening of its second office in Russia, which the company says is: “the latest in a series of strategic investments by Cadence. The office will be located in Zelenograd, “the center of the Russian semiconductor industry … Employees there will focus on providing Cadence Services, and the office will serve as a center of excellence for Cadence virtual CAD services (VCAD). Per the Press Release: “In 2004, Cadence became the first EDA company to open an R&D center in Moscow. The company now employs 140+ engineers to develop technologies that raise the standard of Russian electronic design excellence.”

Wolf-Ekkehard Matzke, Cadence Fellow in charge of the Services business in EMEA, is quoted: "We are very excited to be part of the growing ecosystem in Zelenograd.” Gennady Krasnikov, General Director of JSC Mikron, a Russian fab, is also quoted: "Locating in Zelenograd puts Cadence in close touch to leading Russian IC developers and manufacturers. We are looking forward to working closely with Cadence in the future.”

* The Interoperable PCell Libraries (IPL) initiative announced an “open invitation” to semiconductor companies, foundries, IDMs, and EDA companies to join IPL's three newest technical working groups. IPL says the groups would like interested participants to “contribute to standards on Properties and Parameters, Pcells, and Constraints. The IPL initiative, formed in April 2007 to address PCell interoperability issues, has expanded its charters to address broader interoperability issues with foundry process design kits (PDK) and design flows.”

* Mentor Graphics announced that it has joined the Multicore Association consortium as an executive board member. Let the Press Release remind you: “The Multicore Association is a global non-profit organization focused on developing standards that help speed time to market for products that involve multicore implementations … The Multicore Association supports the multicore ecosystem including vendors of processor IP, multicore chips, operating systems, hardware design and software development tools, as well as application and system developers.”

Multicore Association President Markus Levy is quoted: “As a company that is deeply entrenched in the industry, Mentor Graphics makes a notable addition to the Multicore Association’s Executive Board Mentor’s experience in this industry will help guide this consortium in delivering the most beneficial standards for multicore applications.”

* Nascentric, Inc. announced that NOAH Corp. has been named Nascentric’s exclusive distributor in Japan. Per the Press Release: “NOAH Corporation will provide sales and technical support for Nascentric multithreaded Fast-SPICE product.”

* OneSpin Solutions KK announced it has expanded operations in Japan by moving into a new sales and field applications engineering office in Yokohama. OneSpin also announced it has hired additional field-application staff to support customers onsite.

* OPTIMUM announced that Everett Frank has been named Vice President and General Manager. Per the Press Release: “Everett has been a very important part of OPTIMUM for the past year serving as a part-time consultant, primarily focused on the implementation and continued enhancement of OPTIMUM’s ERP system, as well as helping develop the Program Management and Supply Chain Management departments.”

* Pulsic Ltd. announced that it has appointed Keiichi Watanabe to its advisory board to aid in expanding business opportunities in Japan and Asia. Previously, Watanabe was Vice President for Cadence Japan, and President and CEO of Zuken Redac Inc. a company he took public on the Tokyo stock market. Watanabe also served as President and CEO of Mentor Japan.

* Synplicity announced that the company has joined the Xilinx ESL Initiative. Per the Press Release: “The addition of the Synplify DSP software to the Xilinx ESL design ecosystem underscores the commitment of Xilinx … toward driving technological innovations and solutions that promote high-level, ESL design.”

* Tech Source Media, Inc. announced SCDsource, described as “the first online media outlet dedicated to helping system and chip design decision makers make better informed design and purchasing decisions. The new publication is focused on meeting the critical business and technical information needs of system and chip design engineers.” Richard Goering has been named editor-in-chief of the new publication.

Francine Bacchini, Founder, President and CEO of Tech Source Media, is quoted in the Press Release: “I feel extremely fortunate to be able to channel my business passion for the EDA and semiconductor industries into SCDsource, and to have Richard Goering – with his vast industry knowledge and experience, and fair and balanced reporting – at the helm as editor-in-chief. I envision SCDsource as the high-tech information port of call for the vital EDA and semiconductor communities that so often work without fanfare, contributing the driving technology behind all of the electronic devices we depend on in our daily lives.”

* In other publishing news: Serving in a capacity adjacent to his role as industry pundit, ESNUG’s John Cooley is conducting a survey to determine how folks feel about Synopsys, the company and its tools. If you’re interested in adding your 2 cents, visit DeepChip and follow the instructions there.

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Money Matters …

* Ansoft Corp. announced financial results for Q2 of fiscal 2008, ended October 31, 2007. Per the Press Release: “Revenue for the second quarter totaled $23.4 million, an increase of 14% compared to $20.5 million reported in the previous fiscal year's second quarter. On a GAAP basis, net income for the second quarter was $5.2 million, representing a 41% increase when compared to GAAP net income of $3.7 million in the previous fiscal year's second quarter. GAAP net income for second quarter includes employee stock-based compensation expense of $0.3 million. This compares to employee stock-based compensation expense of $0.6 million in the previous fiscal year's second quarter.”

* Mentor Graphics Corp. announced that Q3 fiscal 2008 results will be below guidance issued on August 23, 2007. Revenue is expected to be approximately $185 million versus guidance of $200 million and non-GAAP earnings are expected to be slightly below break-even as compared to a previously estimated $.10 per share.

* Virage Logic Corp. reported its financial results for Q4 and the fiscal year ended September 30, 2007. Per the Press Release: “Revenues for the fourth quarter of fiscal 2007 were $13.1 million compared to $11.3 million in the previous quarter and $15.0 million for the fourth quarter of fiscal 2006. License revenue for the fourth quarter of fiscal 2007 was $9.9 million compared to $8.2 million for the previous quarter and $11.3 million for the same period a year ago. Royalties for the fourth quarter of fiscal 2007 were $3.2 million compared to $3.1 million in the previous quarter and $3.7 million for the fourth quarter of fiscal 2006.”

* X-FAB Silicon Foundries reported sales for Q3 2007 were approximately 82% higher than those for Q3 2006, increasing from $60 million in Q3 2006 to $109.1 million in Q3 2007. For the fiscal year to date, X-FAB says it generated sales of $295.3 million, up approximately 74% year-over-year. X-FAB Sarawak was included in the comparative figures of the previous year as of September 1, 2006. X-FAB Dresden was included as a consolidated company of the X-FAB Group as of April 1, 2007.

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In other news …

* Actel Corp. announced its Libero IDE, which the company says includes “significant new features, such as power-driven layout, that enable designers to further optimize designs to reduce dynamic power consumption by as much as 30 percent for a typical design… The enhanced analysis environment is the first to give users a comprehensive understanding of power usage in all functional modes of the design … An innovative battery life estimation feature gives portable designers an accurate calculation of battery life based on their FPGA design power profile — a first for FPGA design tools.”

Jim Davis, vice president of software engineering at Actel. “With the advanced layout optimization and power analysis capabilities delivered in Libero IDE v8.1, designers can be even more efficient in the implementation of solutions that consume the lowest possible power.”

* Altium Ltd. announced that NASA’s Johnson Space Center has chosen Altium Designer as its standard electronics design software. Per the Press Release: “The Center’s Engineering Directorate will use Altium Designer as its electronics design standard on both manned and unmanned mission support. These include the Space Shuttle and International Space Station programs, as well as the Constellation program to send astronauts back to the moon … Altium Designer will be used on disciplines as varied as guidance and navigation, electrical power systems, avionics systems, instrumentation, thermal protection, spacesuits and other extravehicular activity (EVA) equipment, aerodynamics and related disciplines, advanced automation systems, and overall systems engineering and simulation.”

* Ambric announced the Am2045B, which the company says offers “higher performance and lower power than its predecessor, the Am2045A … and is the newest in the Ambric Am2000 family of highly scalable, massively parallel processor arrays (MPPAs) using Ambric's award-winning* structured object programming model (SOPM) tools to make massively parallel software development practical for complex embedded systems.” You’ll be hearing lots going forward about all of these topics.

* Cadence Design Systems announced that Micronas selected the Cadence’s Incisive Plan-to-Closure Methodology and Incisive Enterprise Manager for verification planning “after a joint full functional verification audit helped discover and correct process flaws and areas of improvement for Micronas' overall product development process.”

* Catalytic Inc. announced the Catalytic Function Library, which the company describes as “a significant addition to its MCS (MATLAB to C Synthesis) software … The Catalytic Function Library enables MATLAB developers to generate functionally equivalent, re-distributable C code for more than 300 MATLAB functions, including a wide variety of toolbox functions. Algorithm developers now can generate equivalent C models from MATLAB code that take advantage of higher-level MATLAB functions, a formerly manual effort. “

Luc Semeria, Catalytic’s Product Marketing Manager, is quoted: “Algorithm developers use MATLAB because of the power of the vector language and the rich function library. With the release of MCS last year, we addressed getting fast C code from the MATLAB language. Now the introduction of our function library provides a fast path to functionally-equivalent C code for a growing number of MATLAB functions.”

* CoWare and Tensilica announced the integration of Tensilica's Diamond Standard 106Micro, which the companies call “the smallest licensable 32-bit processor core,” with CoWare’s Platform Architect. The Press Release says, “The integration provides designers with the first and most productive ESL 2.0 solution for platform architecture design, platform verification, and software development using Tensilica's processor core with the smallest area, lowest power, and highest performance on the market. This new integration extends the unique relationship between CoWare and Tensilica to the entire Diamond Standard and Xtensa configurable processor product lines.”

* Tensilica also announced a partnership with eASIC Corp. that the companies says will “remove the cost barriers for developing custom embedded SoCs. Through this partnership eASIC now provides free access to Tensilica’s Diamond Standard microprocessor and DSP cores for its free mask charge, no-minimum order ASICs. This unique combination enables embedded system designers to develop Diamond processor-based SoCs for applications in any production volume. Designers will now be able to develop customized, highly differentiated ASIC solutions at a lower cost than FPGA-based embedded systems.”

And so the struggle continues between FGPAs and structured ASICs.

* IPextreme and Motorola announced that IPextreme is bringing advanced Motorola clock generation technology to market in the form of licensable semiconductor IP. Per the Press Release: “The Multiple Reference Clock Generator is a patented digital clock synthesis technology developed by Motorola and is now offered to the global semiconductor market through IPextreme.”

Jim O’Connor, Motorola’s corporate vice president of Motorola Technology Acceleration, is quoted in the Press Release: “Motorola’s rich portfolio of patent technology has been developed over time in our labs. Bringing MRCG to market for licensing is an example of how Motorola’s investment in creating valuable technology can be monetized and leveraged by companies all over the world.”

* Mentor Graphics announced that STMicroelectronics taped out a new set-top box chip using Mentor’s Olympus-SoC P&R system. Thierry Bauchon, R&D Director, Home Entertainment & Displays Group at STMicro, is quoted: “We used Olympus-SoC to tape out an advanced set-top box chip containing 12 million gates and manufactured using an 80-nanometer process. Although this is an extremely complex design with six modes and four corners of operation, we were able to complete the migration to the 80-nanometer process in a fraction of the original three month schedule.”

* Mentor Graphics also announced a collaboration with LeCroy to deliver a complete platform for USB-based protocol applications. Michael Romm, LeCroy’s Director of Product Development, is quoted: “Mentor’s Veloce family of advanced hardware-assisted verification solutions complements our USB test systems. One of our key customers, a world leader in consumer electronic and multimedia systems, can now perform rigorous testing of their latest applications on this integrated, high-performance verification platform.”

* The Open NAND Flash Interface (ONFi) Working Group, the organization dedicated to “simplifying integration of NAND Flash memory into consumer electronic devices, computing platforms and industrial systems, announced the 0.9 draft of the ONFi 2.0 specification to member companies. ONFi 2.0 specs will be released in January, with 71 companies currently supporting development.” Remember that: “ONFi 2.0 defines a high-speed NAND interface that delivers up to 133 MB/second in interface performance.”

Knut Grimsrud, ONFi chairman and Intel Fellow, is quoted: “Previously, the NAND interface was a significant bottleneck in read performance and ONFi 2.0 is solving this issue. Building on our history with this specification, the enhanced performance opens up significant opportunities for NAND in new computing, industrial and consumer electronic applications, with a scalable roadmap for the future.”

* Ponte Solutions and Blaze DFM announced “delivery of the first modeling elements committed to Si2’s DFM Coalition. These contributions are the primary drivers for the critical area analysis and lithography elements of Si2’s DFMC efforts.”

Per the Press Release: “Ponte’s model-based yield analysis technology allows yield sensitivity analysis for identifying critical areas, and will be made available royalty-free to Si2 and DFMC members for standardization purposes, including modification and benchmarking for the next three years. Blaze DFM’s contribution consists of a proposed standard for the interactions between IC design tools and lithography simulation engines. Currently there is no standard interface through which IC design tools can request lithographic analyses of areas of the chip that may potentially contain manufacturing defects, or “hotspots.” If adopted as a standard, this interface would enable IC design tools to seamlessly invoke lithography simulators with directives on what to check for and then allow the simulators to feed back hotspot information that the IC designer can use to locate and correct the defects.”

* Sagantec and Time To Market Inc. announced a collaboration, which the companies says will “jointly deliver complete IC design migration solutions. This joint program combines Sagantec’s layout reuse, process migration, and layout acceleration tools with TTM’s IC design expertise and services … These design migration solutions include migration of complete IC designs to new process technologies, migration of designs from aging fabrication lines to modern fabrication processes, and porting from one foundry to another. These solutions support digital, mixed-signal, custom, or SoC ICs.”

Hillel Ofek, President and CEO at Sagantec, is quoted: “Our customers are reporting breakthrough productivity and time gains using our tools in production for 65nm and 45nm ICs. This new partnership with TTM broadens the access to our technology and opens additional channels for delivering its benefits to a wider market.”

Venkata Simhadri, President and CEO of TTM, is also quoted: “With the increase in complexity and effort necessary to do current layout implementation tasks, we have seen a growing demand for foundry and process portability. Combined with Sagantec’s automated layout migration tools and our design expertise, we can address these demands and provide a solution that is significantly faster and very cost effective.”

* Synopsys announced that Renesas Technology Corp. has signed an “expanded business agreement” that names Synopsys as its leading EDA supplier across the Renesas design flow. The two companies say they will cooperate “to increase the use of Synopsys' technology across Renesas' engineering teams to capture greater productivity and efficiency for the company.”

* Synopsys also announced that Synopsys' DesignWare Wireless USB Device IP has passed the USB Implementers Forum's (USB-IF) Certified Wireless USB Testing and earned the certification logo.

* Test Tooling Solutions Group announced has adopted Ansoft’s PCB Design Suite, which “extends the firm's core design competency, strengthens its pool of intellectual property assets and minimizes time-to-market for new products … TTSG is developing innovative design flows that link process-accurate models of critical, board-level structures with advanced circuit and system simulation.”

* X-FAB Silicon Foundries announced it has “broadened its statistical modeling suite for Monte Carlo simulation for its 0.6 and 0.35 micrometer analog/mixed-signal technology platforms by announcing support for the MunEDA WiCkeD tool family of software tools.” The companies say, “The move reflects ongoing cooperation between X-FAB and MunEDA to reduce the number of required analog/mixed-signal design respins and speed time to market for communications, computer, automotive, consumer electronic and other applications.”

* Zuken says it’s now offering its PCB manufacturing design and verification system, DFM Center; to customers in Europe and North America. Per the Press Release: “DFM Center has already been adopted by leading board makers in Japan, Korea, and Taiwan; including close to 90% of flexible board makers in Japan.”

* Zuken also announced a new version of the company’s desktop PCB design suite, CADSTAR 10.0, which the company says includes a large number of additional “intelligent functionalities for schematic, library and PCB design, tighter integration with FPGA design tools, and the introduction of an alternative schematic front-end solution E³.logic … The use of the E³.Logic database as a back-end solution for CADSTAR PCB design reduces the time spent searching for existing parts, integrates easily with specific MRP, ERP or PDM systems and works with databases that comply with Microsoft's ODBC standard.”