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October 22, 2007
Can a Firm Prosper or Even Survive, If It Gives Away Its Product?
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Can a firm prosper or even survive with a strategy based on giving away their product? In the old days Gillette did very well giving away razors and selling the blades. Today telephone cell phone carriers (Verizon, AT&T, Sprint, etc) give away or at least steeply discount cell phones in exchange for signing service contracts, typically two year contract with early termination fees. Google and Yahoo! provide free services and derive revenue from advertising, an approach that major TV networks and some print media have used for years. Similarly, this website distributes free content and generates revenue from advertising.

Ciranova, a firm that started in 2002, adopted a new business model that has them giving away their PyCell Studio product via Internet download. I had a chance recently to speak about this with Ciranova’s new CEO Eric Filseth.

Would you provide us with a brief biography?

A long time ago I was an analog design engineer. I worked for National Semiconductor on op amp design. I went to work for a small EDA company called Analog Design Tool which was acquired by Valid which got acquired by Cadence. So I ended up working for Cadence. If you count the two acquisitions I worked for Cadence for just under 11 years primarily in the analog area. I was marketing manager for the analog tools area. I left Cadence at the end of 97. I worked for several digital startups. One was Sente which became Sequence. The next one was Silicon Perspective. It was acquired by Cadence at the end of 2001. I’ve been working for Cadence since then. I left a month ago. Monday this
week was my two week anniversary.

Happy anniversary!

It has been an interesting journey. I spent the first bunch of my career in the analog area and the last bunch of years in digital. Most recently at Cadence I was Corporate Vice President of Marketing responsible for all the digital stuff: RTL through mask, place and route, formal verification. All that kind of stuff. Mainly coming to Ciranova is sort of going back to my roots in analog.

What caused you at this point in your life to go from the largest EDA company to a small startup in a small niche market?

First of all I think at some level it was a reasonable time for me to look for doing something else. Our mission at Silicon Perspective was basically to rebuild the digital business at Cadence back to industry leadership. We did that. Cadence had some difficulties in the digital area in the late 90’s. We rebuilt a very strong and industry leading capabilities for RTL to GDS. It was kind of mission accomplished. I’m very proud of the work we did there. I saw this as a new kind of challenge.

One of the things I learned from working in both the analog and digital areas is that the digital area is much more automated then the whole custom slash analog area. In the digital domain engineers say “I would like this PCI Express design but I want it with 5 new features and I want to move it to 55nm technology.” They say that and a computer goes and does the whole thing, whereas in the analog world it is all still done by hand. You have senior design engineers redesigning, very specialized people doing lots and lots of work. A lot of people would say it is very mundane work moving shapes and rectangles around the screen. Stuff is just vastly more automated on
the digital side. I think that there is a vast opportunity to go back and revisit the custom world and do a lot more automation. I thought that was a real intriguing opportunity. Ciranova has interesting technology to do that. So I thought this is something that could be pretty exciting.

What is a PCell (p-cell, PCELL)?

A PCell is a piece of code that an engineer writes which tells a computer how to draw a transistor. Writing those programs (and each one is dozens to hundreds of lines of code) is quite laborious. If you change your silicon process you have to do the PCell again. If you have a 65nm transistor and you want that transistor to run in 45 nm technology, you have to do the PCell all over again. Each type of transistor has its own PCell. If you want a PCell that runs in both a Cadence system and a Synopsys system for example, you can’t have that. You need a different one for each of those. So people end up having to spend lots of time and effort making PCells in order to draw
transistors. Typically what happens is your foundry provides them or if you are a large semiconductor company in a lot of case people will do their own, have big teams of people doing this over and over again. This is one of the things where we think there is real opportunity to make it more efficient.

For PCells what is a supermaster, a submaster and an instant?

A super master is the code, in our case PyCell code. That code exists on disk somewhere in a library. When a chip designer lays down a transistor with a width of 2 and a length of 3 that becomes a submaster. A submaster is a particular representation with a specific set of parameters. If they use a width of 2 and a length of 3 over and over that is a submaster with lots of different instances.

How does a PCELL relate to a PDK (Process Design Kit)?

A PCell is a particular library element within a PDK. A PDK is basically a set of files that a foundry provides its customers so that the customer can do transistor level design. PCell is a major component of a PDK. PDKs contain a few other things like schematic symbols, DRC rule decks and other files necessary to do analog design.

PCells have been around a long time. What problem was Ciranova trying to solve? What issues needed to be addressed?

A good question. PCells have been around almost 20 years. They were pretty revolutionary for their time. We are down in a very low level discussion of automation here. Before PCells engineers literally drew transistors by hand. A PCELL partially automated that. That was a good deal for its time. But PCells have a lot of limitations. The principal ones are that they are not portable from process to process. Each silicon technology needs its own set of PCells, even if the transistors are otherwise identical. If you have a 90 nm transistor, a standard MOS set, and you want to take your design using that transistor into a 80 nm half node technology you need to do all your PCells over again. That’s because the way PCells are done is that they hard code processing information into the PCELL. That’s a major limitation. The second one is that people have a lot of kinds of devices that are not easily represented in PCells. Say you want to do something like a spiral inductor that will have complex via structuring inside of it. It is not very easy to do that in a PCell. So people end up drawing by hand. The third problem is that if you look at all the custom systems out there on the market, they all have a different mechanism for representing how to draw a resistor. Cadence has one way of doing it, Mentor has a different way, and Silicon Canvas a third way. There are
potentially some other tools that will show up that will have different ways of doing it. That means if you have your library of PCells and if you want to run those transistors in a different system, you have to do you PCells all over again. What people want is a PCELL that can run in different process variations and can run in different tool flows and have enough capability so that they can describe these kinds of complicated devices that people have these days.

How do your products address these limitations?

We have developed what we call PyCells which is conceptually the same idea as a PCell, a piece of code that a user write in order to tell a computer how to draw a transistor. The advantage of using PyCells is threefold. First of all, the user writes PyCells in a modern programming language. The one we use is called Python. People in EDA are not familiar with Python but it is widely used for Web 2.0 applications. For example, a lot of Google is written in Python. It is a much more powerful language than what people are used to using for p-cells. Most of them are written in an older language called SKILL. SKILL has been around about 20 years. It is based upon LISP. It was modern in the 1980’s. It is fairly old now. If you look at Python code versus SKILL code, first you need to write a lot less code to do something in Python. Second you can produce a much more complicated structure and complicated behavior easily using PyCells rather than using PCells. The second thing is that PyCells don’t require you to embed data inside the cell that is specific to any given silicon process. That means you can use the same PyCell in multiple silicon technologies. Everything I wanted to do, shrink from 95 nm to 65 nm or if I have several different versions of my 65 nm technology e.g. my regular one, a low power version, a low leakage version and so forth I can use the same
PyCell. People really like that. The third one is that PyCells are interoperable between design flows. There is an industry effort called the Interoperable PCELL Library (IPL) initiative. In fact you can visit their website iplnow.com. There a bunch of companies and we have worked together to build PyCell libraries that will work in design tools from many different vendors. The members of IPI are Synopsys, Magma, Silicon Canvas, AWR, Virage Logic and Silicon Navigator. A lot of people involved. So that is the three advantages: a modern powerful language, process portable and interoperable between EDA design flows.

Reading between the lines it sounds like the process data instead of being embedded is left external to the PyCell. So if you want to port

I think that is a major issue for folks. If you want to take a SERDES design which tends to be done at the transistor level and port that from 65 nm to 45 nm, you need to have PCells for both those processes. Using PyCells you don’t need two you can use the same PyCell. You use a different technology file which is standard kind of data that people have lying around. It just works. You still have to change the layout of where the transistors are and so forth. Typically the layout is going to be done over again but modifying the transistors is much easier.

Cadence and EEsof do not appear to be members of IPI.

Not at this time but we are hoping. I think there is a compelling reason why lots of people should get involved namely the ability of the industry to do more powerful kinds of things with PyCells. That’s going to enable new kinds of design tools, applications and automation in this corner of the world and that will be an opportunity for everybody, all EDA companies and all semiconductor companies. I hope that Cadence and EEsof will get involved.

What is the relationship between you offerings and OpenAccess?

We use OpenAccess (OA) as our core database. Cadence is moving their infrastructure in the custom area to OpenAccess. I think Open Access is a great thing for the industry. Kudos to Cadence. Their vision of building an open architecture would help everybody. It can grow the market for everybody. That’s the right vision. Kudos for them for doing it. OA is going to be a benefit for everybody.

Ciranova was founded in 2002. How big a company is it today?

We have less than 20 people.

If my research is correct, Ciranova has raised about $15 million in venture funding.

That’s correct. We changed business models about two years ago with the Series C funding. At the same time there was a change in direction and strategy. It was at Series C that we went to OpenAccess and open PyCells. That’s our core business right now. That’s the first phase of our core business. It’s about 2 to 3 years old.

One of the things of interest is that PyCell Studio is a free product. What does one get for free?

PyCell Studio is basically a development system for PyCells. It includes utilities, graphics interface, editors and a bunch of things to make it a lot easier to develop them and it includes our API as well which is the core of PyCells.

If I get PyCell Studio for free, are there other not-for-free modules required to effectively use PyCells. Or is there some size or performance limitation with the free version?

No. If you get PyCell Studio you’ve got what you need. Our plan in the future is to offer upgrade get a lot of support for free. If you want a higher level of support then we will do a contract with you. That is a business for us. Most of our focus is on what you are able to do with PyCells. We would like to see lots of use PyCells.

According to Ciranova’s website support for a developer starts at $15k and support for an end user of the developed PyCells at $5K. The price drops with increasing number of users.

That’s correct.

How do you know how many developers and end users a given customer has?

We ask. So far that model has worked very well.

Ciranova plans to have follow-on products in the future but do you have any products available for sale today?

We have not announced any major follow-on products. Our interest lies in the area of automating custom design which is largely manual today. One of the characteristics of the people who design PLLs, Phys, Serdes, DDRs and so forth is that these things have a heavy analog component which is done largely by hand. One of the things analog designers do is that they tend to do a lot of sophisticated manipulations of the transistors themselves not just where they go on the chip or how they are hooked up together but what the transistor actually looks like. So we believe it is important to automate both of those things at once. That’s the kind of area we are doing development in for
future products. One of the good things about PyCells is that they lend themselves well to working with systems at higher levels. We think that is important to the industry.

Is the target market analog, mixed signal, …? Any possible application for digital?

Yeah. The technology we developed with PyCells and that we are working on extending is clearly applicable to analog and mixed signal kinds of things. It is also applicable to other transistor level design applications like memory design for example and for a lot of very high performance digital circuits so microprocessors, customs data paths. Those trend to be done at the transistor level as well. What we have got is applicable as well. That being said, there are a bunch of people in our company who know a lot about analog. It is a natural inclination for us to look at that function.

There are some successful business models based on giving something away and then following up with products and/or services. An example would be Gillette who gave away the razor and made money selling blades.

Red Hat is a good example of that too. Linux is an open operating system, open source and so forth. Yet Red Hat is a sizeable company providing support and capability. In the razor and blade strategy, the razor wasn’t much good without the blade. In the case of PyCell they are perfectly good without the anything else. We are not in a position to come back and say we are going to stealthily charge you for PyCells. That is not the case here. It is more the Red Hat model. A better analogy.

The analog market is relatively small compared to the digital market.

Yes it is. It is kind of interesting. If you look at the semiconductor markets the analog and RFIC markets are about one-half the size of the logic market not including memory. The analog EDA market is much smaller than one-half the size of the SoC, synthesis, place and route i.e. the core digital market. We think that it is an indication that the analog market ought to be a lot bigger. If you look at how things work in digital, at somebody who does system on chip layout, the style that Cadence, Magma, Synopsys and so forth do; if you look at the engineering those companies spend a lot more money on software. Each engineer has hundreds and hundreds of thousands of dollars in tools that they are using. The software is a lot more expensive than the engineer. If you go look in the analog space, they don’t spend nearly that much money on software. The engineer is a lot more expensive than the software they use. We believe the reason for that is that there is just not that much automation. So you have people doing it by hand in analog. The custom and analog space never went through the same transition that digital did where it all got automated. You have people doing the same sort of work over and over again. There is a certain amount of creative work and a lot of repetitive work porting the same voltage regulator from this process variation to that process variation.
We believe that the whole infrastructure is ripe for change. With the application of the right kind of automation technology the market for analog and mixed signal can be much bigger. When you ask why I left my job at Cadence, the world’s largest EDA company, to come here and do this, I see an opportunity to help make that happen and that is very exciting.

If the value statement is that you can make analog designers who make say $150K a year more productive, how much would someone pay for that?

Don’t you have to translate that into a superior end result by some objective criterion say performance or into a faster time to market?

Good question. The answer is some of all of those. At the end of the day it is really productivity that translates to a lot of those things. It manifests itself in several areas. Time to market is very important. The length of time it takes to layout an analog chip is much longer than the time to layout a digital chip. You find all SoCs have some analog component on them. My phone, the one I carry around, has four radios in it. It has Wifi, Bluetooth, CDAM and GSM all at one. That is a lot of analog stuff. The analog stuff takes longer to design than the digital stuff. It gates the time to market. Companies tend to be very clever and very careful in how they organize their projects to try and compensate for that stuff but the analog just takes longer than the digital. There is an impact there. There is another impact on how many people does it take to do this. If you have a team with 10 engineers on it, how many designs can they produce in a year? If you look at any design task there is a certain amount of creative and innovative work there is part of it. And then there is a certain amount of repetitive grunge work, sort of doing the same work over and over again which is not terribly innovative but needs to be done. If you look at what computers are good at, it is taking repetitive, over and over kind of tasks and automating them so that people don’t
have to do that by hand. That is going to be the case as we go to automate analog in the custom world. I don’t think we are going to replace the creative, innovative work of a brilliant analog designer. We are going to take a bite out of the stuff they have to do in order to get that brilliant idea into silicon. There is a certain amount of drudgery that has to be done. I think the industry has an opportunity to automate that.

I understand the greater productivity that PyCells have relative to drawing by hand but doesn’t Cadence have similar capabilities based upon the SKILL language for PCells.

The nature of software engineering has changed a lot in the last two decades. We are in the era of Web 2.0. Twenty years ago nobody conceived what the Internet was going to be. In the early eighties Microsoft Basic was probably the most popular language in the world although most sophisticated things weren’t done in it. When I was in college in the early eighties there was Pascal and things like that. We are just eons ahead of that in terms of modern object oriented software engineering. There is something we can learn in the EDA industry from the cutting edge work being done on the Internet and other kinds of sophisticated applications, financial engineering software and so
forth. In the EDA industry we are good at algorithmic technology but in terms of raw software engineering, the world has moved faster than a lot of parts of EDA. One of the opportunities and this is not the core focus of PyCell, relative component. We have been able to take advantage of that. If you compare and without wanting to do a blow by blow comparison of one language against another, 2007 versus 1987 is light-years of difference. When some of those early languages came out people were driving DeLorens and listening to Duran Duran. It seems like a long time ago.

Ciranova faces a couple of challenges. Whenever I talk to EDA industry executives, they tell me if the use of their product is transparent to existing customers’ design flow, just plug and play, then it is a tremendous advantage. If the prospective customer has to change its design flow, there is considerable resistance. A 10x simulator that takes the same input and produces the same output has a short sales cycle. Wide spread adoption of a new language such as SystemC or Python takes considerable time. How will Ciranova address this issue or am I overstating the problem?

I think you have articulated it well. That is one of the basic challenges that everybody grapples with. It is not different from should I buy a cell phone today or should I wait 3 months for a better one. What you have here is a situation where if I switch to something, it is going to take a certain amount of effort and learning and so forth in order to get there. The question is “Is the thing I am going to switch to enough better than what I’ve got today that it justifies my making that switch?” That is the same for every design flow, every aspect from mechanical to civil, software and so forth. That paradigm is repeated everywhere. I understand it is our job to make sure that we add greater and greater capability to the design process in such a way that we minimize the effort to move over. One of the things, for example with PyCells, is that you can have Cadence SKILL PCells in the same design. So you do not have to choose one or the other. It is really important. If you have an infrastructure you are comfortable with and it runs perfectly well on traditional SKILL PCells but you have one device and every semiconductor company has a few devices that are really hard to model in PCells, you can write a PyCell for that device and use it together with all your existing PCells. You do not have to change your whole environment overnight
to do that. You can adopt PyCells as fast or as flow as makes sense for your environment.

A different view of the same issue. People tend to have budgets for software but possibly not for the support of free software. Is this an issue for Ciranova in getting support contracts? Do you sell direct?

We do. So far we have not seen this to be an issue. It is important to put all of the stuff into context. Most estimates of what it costs to develop a 65 nm chip are many tens of millions of dollars in development. If you are going to make this kind of investment in a silicon chip, for most people support for their infrastructure is not going to be the straw that breaks the camels back. People are looking for ways to be more productive on very complex and expensive chips. If we can add value in that area, the price of service has not cropped up as an issue.

The typical consumer of electronic products, your next door neighbor, buys something. He is more likely to get a service contract or extended warranty as the cost of the product goes up e.g. large screen plasma TV versus a CD player. By analogy won’t it be challenging to get people to pay thousands of dollars to support a free product?

We have not found that to be an issue at this point. It may not be the right analogy. My wife never bought a service contract on a consumer product in her life because they all come with a year’s warranty. I’m not sure it is a good model or not. So far it has not been an issue.

In the software industry there is usually some ratio between the price of software and the price of support (upgrades, bug fixes, phone support), typically around 15%.

This is becoming an increasingly accepted model in the industry. Go back to Red Hat Linux. A lot of software companies have developed very large service organizations, all the way from small firms to Oracle and IBM. The latter have developed very large service organizations not that their software free. People are accepting that service and support as a component of the software business.

I worked for IBM. IBM Service offers to take responsibility for everything, namely hardware, software, facilities and even your IT personnel.

Without wanting to go into excessive detail, I think that’s a model you may see Ciranova doing work at some point as well. The whole problems of PDKs and PCells, most customers just wish it would go away. It is not their value added. Designing a better PCell typically does not mean the difference between winning and losing in the market. People are looking for solutions where this problem can be robust and not be an issue that distracts them from where their core value is. Basically, people look at PCells and transistor models and say that’s where our core IP is.

How much revenue is Ciranova generating?

We do not disclose revenue. We are a private company.

I always ask.

And you should.

Good luck with you business model.

If we can add value people will use us to make chips and we will be able to build a business.

Editor: During this interview I thought I had received a negative reply to my question concerning availability of commercial products but I saw references in the press to such a product. I contacted Ciranova’s VP of Marketing Dave Millman who had been on the interview call for a clarification.

PyCell Studio is the design environment. That is the free product. It has been downloaded probably by 700 different users in 41 or 42 different companies since it was released for free at the beginning of 2006 almost two years ago. That product is free. We offer professional commercial support ala the Red Hat model that we had discussed.

There is a second product we introduced late last year called PCell Xtreme. That product solves different PCell related problems. What it does is two different things. Remember we discussed supermasters, submasters and instances. One thing about submasters, the on-screen representation of PCells in a layout editor is that they are not saved to disk. One of the benefits of PCells when it was invented 20 years ago was it saved disk space because all that was ever saved for a particular instance was a pointer to the code which is very efficient and then the parameters. That’s all that is necessary to describe the transistors. That’s the good news. The bad news especially in an era of cheap, essentially free disk space is that the representation of the transistor is not kept on disk. It is blown away when you close the data base. What that means is each time the data is opened for any operation (and these days there are dozens of operations from DRC to DFM to analysis to simulation to all kinds of things) those PCells need to be evaluated. That’s the problem. The solution is PCell Xtreme. It creates something called persistent PCells. It creates a disk representation, a cache of the PCells. That does two things. It dramatically speeds up the opening of the data base. Customers reporting 100x is common. The other thing it does is it enables SKILL PCells to
be cached and then to be opened in any other tool, any Open Access tool. PCell Xtreme opens the door that had been until now closed to Cadence users who have used SKILL PCells in their design. It allows them to use the tools from any other Open Access vendor.

The product name is PCell Xtreme not PyCell Xtreme. Do PyCells have the same issues?

PyCells use the same mechanism and have the same benefits as PCells and vice versa. PCell Xtreme is not required to operate PyCell Studio but if a PyCell Studio user had PCell Xtreme the opening of the data base would be 100x faster.

Is there any difference regarding the mixture of PyCells and PCells?

There are no issues at all with mixing and no restriction on mixing. You can go from one PyCell with the rest of the chip being PCells. You can have 50/50 or any other mixture. There is no restriction.

What is the list price of PCell Xtreme?

The list price is $4K per end use time based license. The more common way for people to obtain that is through a support contract. If people buy end user support for PyCell Studio that is one of the productivity enhancing tools we give away to commercial support customers.

What about Python IDE (Interactive Development Environment)?

This is a third party product. It is a kind of optional extra. This is a GUI for Python code writing like Microsoft VisualC++ for C++ development. It provides code management, automatic indenting and coloring, bracket matching .. All the housing keeping for writing code and debugging. Lots of debugging tools. We make this third party product available along with some integration with PyCell Studio. It is not required. Some of our customers use it, some do not.

What is the list price of Python IDE?

$180 for one copy of the Pro Version. That’s the same list price as from the third party developer, Wingware.

There was some mention in the press about Ciranova’s intention of making a code donation.

Let me give you the specific details. Earlier this year (July I think) was when we signed the agreement. We made a donation to Si2, the custodians and developers of the Open Access data base, of some cache technology that is related to PCell Xtreme but it is not the source code for PCell Xtreme. This cache technology enables developers for example Cadence could use this for Virtuoso or Silicon Canvas could use this in Laker. It allows anybody that is a member of Si2, essentially all EDA vendors, to down load the source ode and implement that same caching with those speed up benefits. If the all use this code then the caching will be interoperable. That’s another benefit which
would have to be implemented by all the vendors. There is a benefit to having a cache and even greater benefit tin having an interoperable cache. We donated for free open source use the source code for implementing caching within an EDA tool.


Red Hat was cited as an example of a successful company whose business model involves giving away product. In its last fiscal year, the period ended February 28 in 2007, Red Hat’s revenue was $341M in subscriptions, $59M in training and services for total revenue of $401M and a net income of $59M.

In its 10K report Red Hat states

“Open source software is an alternative to proprietary software and represents a different model for the development and licensing of commercial software code than that typically used for proprietary software. Because open source software code is freely shared, there are customarily no licensing fees for the distribution of the open source software. Therefore, we do not recognize revenue from the licensing of the code itself. We provide value to our customers through the aggregation, integration, testing, certification, delivery, maintenance and support of our Red Hat enterprise technologies, and by providing a level of scalability, stability and accountability for
the enterprise technologies we package and distribute.”


“We have continued to build our open source architecture by expanding our enterprise offerings and introducing new systems management services, middleware, clustering capability, file management systems, directory and certificate technologies and enhanced security functionality.”

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  • AWR Announces Record Sales and Profits for First Half of Fiscal Year

  • Saifun Adopts Pulsic Technology Following Rigorous Trial

  • Berkeley Design Automation's Analog FastSPICE(TM) Selected by Fujitsu for All Next-Generation Analog/RF& Mixed-Signal IC Design

  • MediaPhy Licenses Tensilica's Diamond Standard 108Mini Processor Core

  • Anchor Bay Adopts Cadence Incisive XTREME III System for Verification of HDTV and Digital Video Products

  • Carbon Design Systems to Participate at ARM Connected Community Technical Symposium

  • AWR Announces Record Sales and Profits for First Half of Fiscal Year

  • Sequence to Host DFP Seminar November 8th in Japan

  • CLK Design Automation Acquires Synchronous DA

    Other IP & SoC News

  • Catalyst Semiconductor Rolls Out Dual, 300mA Low Dropout (LDO) Regulator

  • Zarlink Expands Voice Processing Portfolio by Introducing Voice Messaging and Prompting for Advanced Speakerphones

  • Atmel Appoints New Managing Director for Secure Microcontroller Solutions

  • Genesys Testware Adds Automated Batch-Mode Diagnosis and Characterization of Embedded Memories

  • Intel Posts Record Third-Quarter Revenue And 64% Rise In Operating Income

  • Pro Design Goes Japan

  • Cavium Networks' New OCTEON(TM) Plus CN58XX Low-Power Series Breaks the 1 Watt per Core Barrier

  • fimicro Designs Ramtron's 4Mb F-RAM Memory Into Its New PC/104-Compliant Single Board Computer and Smart I/O Modules

  • Tundra Semiconductor Introduces Multi-Standard Serial RapidIO Switch with PCI Bridging and FPGA Interface [

  • GDA Technologies Announces Collaboration With California Micro Devices to Develop CM5100 for Mobile Handset Designs

  • Freescale RF Technology Breaks the 1 kW Barrier with 50V RF Power LDMOS

  • Freescale Adds Two SMARTMOS(R) Devices to High-Side Switch Portfolio

  • Intel Extends Power-Saving Chipset to Embedded Systems

  • Freescale and Continental Collaborate on Multi-Core 32-bit Microcontroller for Electronic Braking Systems

  • eRide Introduces Its Ultra High Sensitivity Opus III eZ(TM) GPS / A-GPS Chip

  • Toshiba Expands UMOS V-H Series High-Efficiency Switching MOSFETs for Synchronous DC-DC Converters

  • Xceive and Jazz Semiconductor Team to Deliver High Performance Analog-Digital Single Chip Silicon TV Tuners

  • Cypress Introduces 4-Mbit nvSRAM Built on 0.13-Micron SONOS Process

  • DFT Microsystems Strengthens Executive Team

  • RT Logic Announces Availability of New High-rate Digital/Analog Recorder

  • Atmel and AST Announce Collaboration for Systems-on-Chip Based on Atmel's AT91CAP Customizable Microcontroller

  • MagnaChip Reports Preliminary 3Q07 Revenue

  • 3Plus1 Technology Announces Availability of CoolEngine Multicore IP Family for Mobile SoC Products

  • ONFi Adds Block Abstraction to NAND Flash

  • Renesas Expands SuperH(R) Family, Adding SH7730 Group With a 200/266MHz SH-4A CPU Core for Industrial Applications and a Wide Range of Others

  • Danaher To Acquire Tektronix, Inc. for $38.00 Per Share, or $2.8 Billion

  • Power Analog Microelectronics Delivers Industry's First High-Voltage LED Driver with Integrated 3A Power MOSFET for Driving up to 72 White LEDs

  • ARM Works With Intel to Deliver Increased System Protection for Flash Memory Devices

  • Broadcom Leaps Ahead of the Competition with the World's First '3G Phone on a Chip' Solution

    You can find the full EDACafe event calendar here.

    To read more news, click here.

    -- Jack Horgan, EDACafe.com Contributing Editor.