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The volume of news is up and to the right in these early weeks of the Fall Conference Season. It’s your call as to what’s important, but I’m picking Eric Filseth’s leap from Cadence to CiraNova, the Ponte/Blaze DFM contributions to the newly-announced Si2 DFM Coalition, Synopsys’ DesignWare System-Level Libraries, and Solido Designs’ newly announced STAT design suite, to Win, Place, Show, and Whatever Comes After Show for the news of note over these last several weeks. Of course, if you count yourself among the sibyls and seers, you might also choose the Microsoft-Cadence patent cross-licensing algorithm as the one that may morph the EDA industry into something else. Only time will tell.

Meanwhile, like many of you I’ve been hanging out at conferences over these last several weeks. After visiting CDNLive!, the FSA Suppliers Expo, and the EDA Tech Forum – all in Silicon Valley – I made my way to the East Coast to spend a day at the Embedded Systems Conference in Boston. You’ll find a brief sketch of my impressions from those four conferences below, along with some personal conclusions abut what makes tech conferences succeed. Again, only my opinion. Only time will tell if these four conferences, or an others for that matter, continue to grow and/or thrive in the coming years.

Chapter 1: Four on the Floor - CDNLive, FSA Suppliers Expo, EDA Tech Forum & ESC
Chapter 2: Coming soon to a theater near you
Chapter 3: Filseth Takes over at CiraNova
Chapter 4: News of note

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Chapter 1: Lessons Galore from Four on the Floor …

If you’re a tech-conference junky, these last several weeks offered up multiple opportunities to feed that addiction. Cadence’s User Conference – CDNLive!, – lit up the East End of the San Jose Convention Center from September 10th to 12th and included keynotes, sessions, 9 technical tracks, a lively exhibition hall showcasing 50+ companies, lotsa food, and a fabulous conference bag. The company said 700+ friends and followers from 180+ companies and 16 countries were on hand to participate in the celebration.

The stated thesis of the show was simple: Collaboration.

The unstated thesis was far more complex: Is the Vendor Specific User Conference (VSUC) the future face of confabs in EDA?

Monday morning’s opening at CDNLive! showcased Cadence President & CEO Mike Fister, as well as Cadence Technical Guru Alberto Sangiovanni-Vincentelli. Proceeded by some downright floor-shaking house beat, Fister’s was a pump-it-up presentation that laid out the width and breadth of the Cadence offerings, culminating with an intro to the company’s new DFM uber-initiative. Although decked out in trendy all-black-sans-tie, Fister claimed to be long in the tooth and able to remember the Good Old Days, Holy Gosh, when WYSIWYG. Nowadays, he said, Cadence is co-opting the idea to offer DFM-aware WYDIWYG. He closed his lengthy keynote presentation by proclaiming that Cadence is moving electronic design from the realm of art to that of science, and earned a solid round of applause from an almost-SRO crowd fresh off of their free breakfast in the ballroom next door. By the way, although Fister shared the stage last year with the San Jose Convention Center Fire Alarm, happily this year his was a strictly solo act.

Fister was followed on September 10th by Sangiovanni-Vincentelli. Reaching out to the right brain of his distinctly left-brain audience, Dr. S-V modestly announced, “My talk is different from Mike’s,” and proceeded to invoke Caravaggio, Picasso, SPICE, Italian racing cars, bifurcations in the market, expensive jewelry, teen-tech fashion, academia, money-making machines, physics, economics, parallel architecture, John Hennessey, ICs, IC content in cars, the millions of lines of code in embedded systems, software designers, hardware designers, concurrency, heterogeneity, ubiquitous electronic connectivity, privacy and the law, evolution, Jan Rabaey and synthetic biology. He ended his comprehensive philosophical treatise by noting that optimists see electronic design moving from craft to science, but realists know “we’re still in the craft age.” Sangiovanni-Vincentelli challenged his audience to examine the first-principle implications of all that they do, to be bolder, smarter, more inspired, more innovative, and to look to higher levels of abstraction. His message: You have the power to reinvent your world. Seize that power. Carpe Diem.

Hard act to follow? You betcha, but time knows no master, so moving along …

By Wednesday, September 12th, not only was CDNLive! still going on under the Big Top in San Jose, but the Santa Clara Convention Center was simultaneously hosting the one-day FSA Suppliers Expo and the equally-one-day Mentor Graphics-driven EDA Tech Forum. Estimates of 2000 in attendance at the Expo down in the West End of the Santa Clara venue, and 1200 in attendance at the Forum up in the East End, were hard to confirm. But there were definitely lots of folks milling around in the hallways, with a fair number of them clearly attempting to be in two places at once.

When you initially walked into the Santa Clara Convention Center, the first question was what brain surgeon decided to have both of these events on the same day and in the exact same building? Was it cooperation or lack of communication between the folks driving the Suppliers Expo and the folks driving the EDA Tech Forum? That conundrum was compounded by the congenial announcement that came down from some building-wide PA system acknowledging that, yes indeed, there were two conferences going on and everyone was invited to check out the FSA Expo for starters, and then return to the Tech Forum venue for the fabulous 10 AM keynote.

Well that certainly resolved my dilemma, so I decided to follow those marching orders. I started in the East Lobby and registered easily for the Tech Forum. Then I crossed Check Point Charlie to the West Lobby to register and check out the sumptuous food cheerfully welcoming early arrivals to the FSA Expo. Then things bogged down a bit, as I had to stand in line with at least 40 other people to wait for the sole clerk processing Exhibitors/Speakers/Press registrations. Frustrating because the other 10 clerks for the Pre-Registered sat idle – their lines were empty.

Finally, however, we all made it onto the show floor and things were great there. Very neat. Very tidy. Very upbeat. A decent amount of traffic, and everyone relaxed and ready to share their info. Scads of foundries, plus a huge dollop of fabless and IP companies. All told, it looked far better and more complete than last year’s FSA Expo down in San Jose, so kudos to all involved for the facelift on the event. There was also a lengthy panel about IP going on in the nearby ballroom during that first hour, moderately attended by the look of things, because it seemed the real action at the Suppliers Expo was going to be out on the show floor for the bulk of the day.

After I finished my tour of the West End, I packed up my badge, my bag, my numerous press kits, and a chotchky or two and made my way back to the principle theater on the East End for the EDA Tech Forum 10 AM keynote. There, surrounded by the largest number of palm trees I’ve ever seen on a single high-tech convention stage, Tech Forum Editor-in-Chief Paul Dempsey pleasantly welcomed everybody to the show and introduced the speaker, NASA’s Dr. Steve Squyres, Principal Investigator of the Mars Exploration Program, an adventure personified by two robotic rovers named "Spirit" and "Opportunity.”

Oh my gosh – what a fabulous keynote! With at least 500 people in the audience perched on the edge of their seats, Squyres ran us through the history, design, simulation, launch, journey, landing, control, exploration, and overall ups and downs of the plucky Mars rover companions that are still, 3 years into the program, patiently working away at an ever-expanding agenda of tasks sent to them from their masters at JPL, extending day-by-day their now-legendary 60-day mission to explore the surface of the most forlorn planet in the neighborhood for as long as those crazy robot twins can last.

Squyres’ talk was compelling, particularly as there had been breaking news that very morning that the duststorm-afflicted “Spirit” had been rejuvenated after its life-giving solar panels had been swept clean by the very winds that had deposited the photon-forbidding dust coat in the first place. Kudos to the folks at the EDA Tech Forum for hosting such a talk. Great speaker. Hugely interesting topic. Profound implications for both science and engineering. And a springboard to follow-on conversations on a host of other topics normally commandeered by theologians, philosophers, and artificial intelligence aficionados.

Hard act to follow? Well, yeah maybe …

But then there was the Embedded Systems Conference in Boston. Having never been to the Hynes Convention Center in Boston‘s Back Bay, it was a challenge just to find the ESC Registration Desk in that cavernous architectural behemoth. However, once one got one’s bearings, it turns out Hynes is actually a very user friendly place. It’s vertically integrated, so rather than having to walk miles and miles to get from one event to another, you go up and down elevators or stairs or escalators to reach your final destination. Very civilized.

If you were only at ESC for one day, hopefully it was September 20th. Because on that day, you could have enjoyed several fascinating keynotes regarding Privacy and Technology offered up by Jim Harper from The Cato Institute and Ben Anderson from the Technology Policy Counsel in conjunction with the co-located RFID World.

Then you could have rushed over to a mainline teaching session associated with ESC offering practical tips to real-world software developers on how to design and code multi-threaded applications for the burgeoning, highly underutilized domain of multi-core chips. That session, ably taught by Michael Anderson, started off by looking at what’s a thread anyway, versus a process, versus multi-tasking. Very interesting, particularly when followed by a quick visit to the noisy ESC show floor where a Harley Davidson in the Intel booth sat gleaming next to an Intel booth barker decked out in rough-and-tough chopper duds cajoling passerbys to consider: “Power, Man! That’s what Intel’s multi-core chips get you. Power!”

Too bad that particular chopper dude hadn’t attended Anderson’s far more pedestrian, but far more technically accurate: “Getting the Most of Multi-core Processors” in the previous hour upstairs.

Continuing on September 20th, your afternoon at ESC would have been swept up with meeting vendors on the Exhibit Hall Floor. My schedule included IAR, Parasoft, Safenet, The MathWorks, and Carbon Design. I also managed to dash over to the Sheraton Hotel, adjacent to the Hynes Center, to catch a 3 o’clock panel ably moderated by industry analyst Erach Desai at America Growth Capital‘s 4th Annual Emerging Growth Conference.

Desai’s panelists included the CEOs of Denali, eSilicon, and Magma – specifically, Sanjay Srivastava, Jack Harding, and Rajeev Madahavan – who engaged in a very interesting discussion with Desai. Too bad, their time was limited to 45 minutes, because it could have easily gone on for another hour and remained vital. Desai threw out the suggestion that an integrated electro-mechanical design flow was somewhere in the near future for an expanded EDA, but his three CEO panelists were not quite ready to embrace that vision. A lively conversation ensued, nonetheless, which has been archived on the web. Go find it and listen in.

So, after the brief foray to the Sheraton, it was back to ESC in the Convention Center, and more opportunities to explore the floor and/or attend sessions. Then it was time to go, time to type this up, and time to draw some conclusions about what makes or breaks technical conferences. Why we like some, and dislike others. Why some succeed and some do not. Here’s my list. I’m sure you could assemble your own.

1) Make the overall convention space a pleasant space, and choose a space that’s located within easy reach of the target population of attendees.

2) Provide extraordinary keynote speakers, people who can speak on topics that start with the engineering specific to the conference and expand to include the larger scientific and/or societal implication of that technology.

3) Provide a rich agenda of tutorials and how-to sessions. People want to learn something useful, as well as being entertained when they come to a conference.

4) Limit the amount of stuff crammed into the show bag. Nobody really wants all that marketing collateral and most of it ends up in the recycling bin anyway.

5) Limit the number of chotchkies on the Exhibit Hall Floor. It makes for a more professional looking conference and nobody needs that junk either.

6) Limit the Exhibition part of the conference to just two days. Three days is too long for any show – both exhibitors and attendees start to drag. Far better for exhibitors to enjoy the buzz of full hallways because people feel the time to visit the show is limited, rather than have to endure the muting effect of too much time and too few visitors. Attendees also enjoy the show far more when there are crowds a’buzzing between the booths, which will happen if the exhibition time is compressed.

7) Appeal to an international audience. Regionalism is so last century. It’s the 21st century now. Embrace globalization. It’s the buzz.

8) If young people aren’t coming to the conference, go back to the drawing board. They’re the ultimate buzz.

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Chapter 2: Coming soon to a theater near you …

Need more conferences to feed that tech-show addiction? You’re in luck:

* EDAC/CMP Future of Media Forum – September 26th in Santa Clara

* Xilinx Serial Connectivity Seminar – September & October across North America

* ARM Developers’ Conference – October 2nd to 4th in Santa Clara

* SAME 2007 Forum – October 3rd & 4th in Sophia Antipolis

* VLSI-SoC 2007 – October 15th to 17th at Georgia Tech in Atlanta

* EDAC Compliance Forum – October 18th in Santa Clara

* 17th Annual IMEC Research Review Meeting – October 18th & 19th in Brussels

* ITC 2007 – October 21st to 25th in Santa Clara

* ICCAD 2007 – November 5th to 8th in San Jose

* 2007 International SoC Conference – November 7th & 8th in Newport Beach

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Chapter 3: Filseth takes over at CiraNova …

Thanks to help from Wired Island’s Mike Sotak and a delayed flight to Boston on September 19th, I had a chance to sit in the airport and chat by phone with the newly anointed CEO of CiraNova, Eric Filseth, recently of Cadence. I asked Eric if he’s had the longest tenure at a single company of anyone currently alive in Silicon Valley – 17 (accumulated) years at Cadence. He laughed and said, “Nope. My brother’s been at LSI Logic for 24 years.” Wow. Talk about your longevity genes.

Eric told me he’s really proud of what he and his colleagues have accomplished at Cadence over the last 6 years, since he came back into the company via the Silicon Perspective acquisition. “We had hit a point where Cadence’s position in digital was very shaky. Now they’re one of the leaders in digital – tied for leadership, in fact. Today, the Cadence tools are very competitive and arguably Best in Class for a lot of designs. Of course, I’m proud of the work we did in the analog area, as well, and the Low Power Initiative, and the more recent work on the DFM portfolio. Although it’s a good time right now for me to be moving back into a small company, I’m very optimistic about what Cadence is doing these days.”

Given CiraNova’s position in analog, I had a trick question for Eric: “Is there such a thing as analog IP?”

Filseth laughed and said, “Not yet.” He paused and added, “Well, there is some, but the problems in analog are very hard. In the digital world, everything is very, very automated, but in the analog world it just isn’t that way. It’s still mostly done by hand and the concept of IP as you consider it in digital – take the RTL and port it to this design or that process – is not there. In analog, it’s still a manual thing for PLLs, and amplifiers, and so on.”

He added, “There’s been so much focus on digital SoCs, and things like place and route, there’s been a lot less time spent on analog. Now digital design works fantastically well. You can get a junior engineer with only a couple years’ experience designing thousands of gates a day. Just think about it. Over the last 20 years, we’ve had 4 or 5 generations of digital architectures developed, but in analog people are still doing things the way they did it 15 or 20 years ago. Clearly there‘s an opportunity here, and CiraNova is well positioned to take advantage of that opportunity.”

What makes CiraNova think they can suddenly change things that have been becalmed for so long? Filseth said, “It will be hard to do, but the OpenAccess movement is making it possible to do custom design without being as tied to the database of your tools, and the low-level aspects of the silicon. Also, the new IPL [initiative] will help. For digital folks, IPL is not really on the radar screen yet, but the combination of OA and IPL is going to make it a lot easier to make progress in analog.”

But what does about the shortage of analog engineers coming out of the schools? Hasn’t digital design been so much sexier for so long that nobody‘s studying analog anymore?

Filseth agreed there’s a problem: “Back when I graduated from college, analog guys were just a small minority of the class, only 10 percent, whereas 90 percent of the class were in digital. Analog and RF [together] were a narrow niche, only used in the military and not very well known. Now, however, it’s totally the opposite. So I hope it’s turning around in the colleges.”

So, I asked, is the headline: “Filseth Brings Sex Appeal back to Analog!” Eric laughed out loud and insisted the real excitement today is in making those analog people more efficient.

Okay, then what about those hard-core analog guys who refuse to yield to automation and 21st century EDA sensibilities? Filseth acknowledged, “Yes, a lot of analog design is still a creative effort and I’m not sure you can ever completely automate the process -- taking an existing analog design and figuring out how to lay it out with a different footprint. Nonetheless, it’s a process that cries out for automation, and [if we can do it], we can let those scarce analog designer resources do what they do best.”

Okay, I said, “Then, just 2 more questions. Is OpenAccess really open?”

If Filseth thought the question was rude, he didn’t show it. He answered easily and straightaway, “Yes.” And then, “Kudos to Cadence for doing a good job for the industry with OpenAccess.”

“Second question,” I said. “Do you get the corner office?”

Now Filseth really laughed: “We’re kind of a small company, so there‘s no corner office yet. But, I do have my own white board!”

[Editor’s Note: In addition to Silicon Perspective, Filseth also worked at start-up Sente. He began his career as an analog design engineer at National Semiconductor. Filseth has a BSEE from Stanford and an MBA from UCLA.]

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Chapter 4: News of note …

* Voltaire Ltd. and Synopsys, Inc. announced they’re developing a high-performance compute (HPC) cluster for semiconductor mask data-preparation (MDP) applications. Per the Press Release: “The HPC solution, which consists of the Synopsys CATS MDP solution running on a high-performance compute infrastructure with Voltaire InfiniBand and DataDirect Networks' storage, reduced MDP turnaround time by up to 4X compared to clusters using Gigabit Ethernet … Originally developed for Synopsys’ in-house testing and now available to customers, the new HPC solution delivers high-performance file I/O using the Lustre parallel file system from Cluster File Systems (CFS), DataDirect Networks' S2A (Silicon Storage Appliance) and the Voltaire Grid Director 10 Gigabits/second InfiniBand switches, which use Mellanox Technologies' InfiniBand silicon solutions.”

* ViASIC has named Lynn Hayden as President and CEO, while he continues on as Chairman of the Board. Prior to joining ViASIC in 2003, he was President and CEO of Coiltronics, a company he founded in 1977 after graduating from Central Michigan University. Hayden sold Coiltronics to a “large multinational corporation in 1997.”

* VaST Systems announced that Marios Zenios has been appointed Strategic Advisor for Automotive. He has 20 years of automotive, telematics, and communications experience, and previously served in an executive capacity at Motorola.

* U.C. Santa Cruz Extension says it’s partnering with TTM and Cadence Design Systems (I) Pvt. Ltd (“the Indian arm of Cadence Design Systems, Inc.”) to offer a certificate program in VLSI design engineering in New Delhi, “building on the success of the branches in Hyderabad and Bangalore.” Please note – the TTM Institute of Information Technology (TIIT) is a “wholly owned subsidiary of Time To Market Inc.”

* The MathWorks introduced RF Blockset 2, which the company says “extends Simulink with a library of blocks to model the behavior of linear and nonlinear RF components – filters, transmission lines, amplifiers, and mixers – by supporting the widespread Agilent standards for large signal-scattering parameters in system-level verification models.” The take-away here is that there are a boatload of standard data file formats for network parameters and noise properties, and RF Blockset 2 helps engineers deal with that nightmare.

* Tensilica and Chip Estimate announced that Tensilica has joined the Chip Estimate Prime IP Partner Program. Steve Roddy, VP of Marketing and Business Development at Tensilica, is quoted: "By using ChipEstimate.com for centralized IP information and chip planning tools, designers will be able to find and see the impact and advantages Tensilica's IP offers in a chip plan context."

* Tensilica has its own partner program, as well, and just announced that P-Product has joined the Tensilica Xtensions Partner Network.

* Takumi Technology announced it’s collaborating with Chartered Semiconductor Manufacturing to validate Takumi’s Enhance DFM optimization software on Chartered’s 65-nanometer process implementation of the Common Platform technology. Per the Press Release: “Patterns tested on wafers manufactured using 65-nanometer process technology from Chartered showed opportunities for gate CD variation improvement and enhanced detection of lithography-related violations.”

* Synopsys announced its DesignWare System-Level Library. Some of the details: “The library provides high-performance SystemC transaction-level simulation models (TLMs) for assembling virtual platforms, including instruction set simulators (ISS), and TLMs of Synopsys' DesignWare Cores and ARM AMBA interconnect components. All DesignWare System-Level Library models are written in SystemC and work in IEEE 1666 (SystemC) compliant simulation environments … The DesignWare System-Level Library features more than 50 TLMs.”

Gary Smith, Chief Analyst of Gary Smith EDA, says the move kills two birds with one stone: "The largest ESL market today is the software virtual prototype, and it could also be the fastest growing but for two issues. First is a standard modeling language and second is a critical mass of models using that language. Synopsys' introduction of the SystemC based Transaction-level models in their DesignWare System-Level Library addresses both of these."

* Synopsys also announced its DesignWare USB 2.0 nanoPHY IP has received USB logo certification, and its PCI Express (PCIe) PHY IP passed compliance testing when implemented in SMIC's 130-nanometer G process technology.

* Synopsys announced, as well, that UMC is using Synopsys' memory IP development automation environment.

* Meanwhile, Synopsys and Signal Integrity Software, Inc. (SiSoft) announced integration of SiSoft's Quantum-SI tool and Synopsys' HSPICE simulation tool. Todd Westerhoff, VP of Software Products at SiSoft, is quoted: "Quantum-SI extends HSPICE to provide a comprehensive design and analysis environment for pre- and post-route analysis that allows customers to seamlessly mix IBIS and transistor-level models.”

* Solido Design Automation announced new software, SolidoSTAT, designed to address the problem of preventable parametric yield loss for transistor-level statistical design and verification. The SolidoSTAT suite includes 5 tools: SolidoSTAT Sampler accelerates traditional Monte Carlo analysis through parallel processing and high-efficiency sampling algorithms. SolidoSTAT Characterizer pinpoints sources of yield and performance loss in the design. SolidoSTAT Circuit Enhancer automatically explores sizing alternatives. SolidoSTAT Tradeoff Analyzer mines Sampler results, without additional simulations, to identify tradeoffs between specifications that improve yield. SolidoSTAT Visualizer converts raw data from all the analyses into dynamic visual representations.”

Resve Saleh, Professor of ECE at University of British Columbia, is quoted: "Three goals of all design teams are to avoid yield loss and over-design, improve design robustness, and maximize designer productivity … Solido has produced an elegant solution to address these key areas for transistor-level nanometer designs."

* SoftJin announced that Blaze DFM is now a customer. Steffen Rochel, VP of Engineering at Blaze, is quoted: “Wherever possible, we leverage existing technology and infrastructure. That’s what drove our selection of the OpenAccess database and our licensing of EDA software components from SoftJin.”

* S3 (Silicon & Software Systems) announced the availability of silicon results for its portfolio of high-performance, mixed-signal converter IP at the 65-nanometer technology node. Mike Murray, S3 General Manager, Mixed Signal IP, is quoted: “We have a deliberate strategy to address the needs of the high growth consumer applications market by broadening our IP portfolio at the 90 nanometers, 65 nanometers, and lower technology nodes. S3's first time success in migrating this high performance mixed signal converter IP portfolio to the 65nm node marks another industry first for S3 at this node.”

* Silicon Integration Initiative (Si2) announced the Design-For-Manufacturability Coalition (DFMC), which the organization says will “build on previous efforts to ensure that ICs can be manufactured in accordance with the original design. Founding members include Cadence, Freescale Semiconductor, IBM, Ponte Solutions, Samsung, Sagantec, ST Microelectronics, and Texas Instruments, with other members are expected to be announced soon.”

* Si2 also announced that Ponte Solutions and Blaze DFM have made “important technology contributions to the DFMC … Ponte's model-based yield analysis technology allows yield sensitivity analysis for identifying critical areas. Blaze DFM's contribution consists of a proposed standard for the interactions between IC design tools and lithography simulation engines.”

* Ponte Solutions and Blaze DFM used alternative words: “These contributions are the primary drivers for the critical area analysis and lithography elements of Si2's DFMC efforts … Currently there is no standard interface through which IC design tools can request lithographic analyses of areas of the chip that may potentially contain manufacturing defects, or ‘hotspots.’ If adopted as a standard, this interface would enable IC design tools to seamlessly invoke lithography simulators with directives on what to check for and then allow the simulators to feed back hotspot information that the IC designer can use to locate and correct the defects.”

* Pulsic Ltd. announced a patent from the U.S. PTO for Pulsic’s spine-and-stitch routing technology, "Method of automatic shape-based routing of interconnects in spines for integrated circuit design.” The company says the technology optimizes the layout of long aspect ratio nets found in memory design and “automates a previously manual process.”

Also per the Press Release: “Spine and Stitch is a linear routing style used to connect custom cells placed in channels or spine areas of memory. These routing areas are often found in the layout of peripheral logic for DRAM, SRAM and Flash memory, and are characterized by extreme aspect ratios, producing long and narrow routing footprints. The spines are very long and the stitches are shorter orthogonal tracks, which gridded routers are unable to guarantee.”

* PLDA announced a new business division, Application IP (AIP), which the company says “will leverage PLDA's high speed bus IP core designs into key vertical markets.”

* Parasoft Corp. announced extended support for its C/C++ tool, Parasoft C++test. Sergei Sokolov, Professional Services Manager at the company, is quoted: “Parasoft C++test integrates multiple technologies, enabling developers to start verifying code as soon as it is completed – even if the target hardware is not yet built or available for testing.”

* OCP-IP (the Open Core Protocol International Partnership) announced 5 new members: Averant, HDL Dynamics, Korea Electronics Technology Institute (KETI), PLS, and Silicon Laboratories. Per the Press Release: “The new members represent a breadth of technologies, illustrating the combined industry-wide acceptance and adoption of the OCP standard.”

* Nascentric announced $7.2 million Series C financing and a new investor, Intel Capital. Per the Press Release: “Existing investors Austin Ventures, Silverton Partners, Needham Capital and EDA veteran Jim Solomon also participated.”

* Nikon and Synopsys announced that Nikon's optical lithography exposure tool data is included in the latest release of Synopsys’ Proteus OPC software. Per the Press Release: “As part of an ongoing collaboration, the two companies developed an embedded scanner parameter module, which delivers the manufacturing-aware OPC and RET lithography simulation models needed for 45-nanometer and below IC manufacturing … The newly developed interface allows Proteus modeling customers to automatically access Nikon's proprietary scanner information, including such higher-order lithographic effects as polarization, flare, synchronization, and various aberration data.”

* MIPS Technologies announced that Opulan Technologies has “extended its commitment” to MIPS architecture and cores, and is using the MIPS32 4KEc hard IP core for its next-generation broadband-access SoC designs. Per the Press Release: “Developed by MIPS Technologies' Shanghai R&D facility and targeting TSMC's 130-nanometer process, the 4KEc hard core is a technology-specific implementation of the synthesizable 32-bit 4KEc processor. Opulan is the latest China licensee to develop MIPS-Verified designs, further establishing Greater China as MIPS' fastest growth market worldwide.”

* Microsoft and Cadence Design Systems announced a patent cross- licensing agreement, which allows “broad access to each company's respective patent portfolios to facilitate future technical collaboration in areas of common interest to both companies … The companies' exchange and implementation of patented technologies will span many areas and give both companies greater freedom to innovate.”

R.L. Smith McKeithen, Senior VP and General Counsel at Cadence, announced: "Both Cadence and Microsoft are leaders in their respective technology space and in the software industry – we have a common interest in fostering innovation within the industry and leveraging those innovations to provide pioneering solutions for our customers. IP licensing is a collaborative way to spur innovation, and this agreement is a natural extension of this goal."

Horacio Gutierrez, VP of IP & Licensing at Microsoft, is quoted: "We are delighted to be collaborating with Cadence, the world's largest maker of software used to design integrated circuits and electronic systems … This cross-license agreement is a perfect demonstration of how licensing IP extends the reach of modern innovations across companies."

* Mentor Graphics announced that M. Sharma, W. Cheng, T. Rinderknecht, L. Lai and C. Hill of Mentor Graphics have received the ITC Ned Kornfield Best Paper Award for their paper entitled, “Signature-based Diagnosis for Logic BIST.” Per the Press Release: “The paper describes how a signature-based-only diagnosis for logic BIST achieves diagnosis resolution with manageable diagnosis run time while eliminating the complexities of traditional logic BIST diagnostic approaches.”

* Mentor Graphics also announced the PADS I/O Designer for the PADS product user community. Henry Potts, VP and GM of Mentors' Systems Design Division, is quoted: "Users of high-end FPGAs report time-to-market reduction and systems performance improvement of up to 50 percent, and reductions in PCB layer counts resulting in reduced product costs. With the continuing trend in electronic products of using even more high-end FPGAs, the impact of providing I/O Designer to our PADS users is significant."

* Mentor Graphics announced, as well, the launch of the Inflexion Platform Multimedia Feature Pack for Nucleus OS. Per the Press Release: “Inflexion Platform UI … enables the agile creation and customization of visually compelling, easy-to-use interfaces for consumer electronic devices such as mobile phones, personal media players, and set-top boxes. Inflexion Platform Multimedia Feature Pack extends this capability, enabling rich audio and video content to be incorporated easily throughout a device's interface, without the need for programming or scripting.”

* Meanwhile, Mentor announced that MediaTek is using Mentor’s 0-In Formal Verification technology for MediaTek’s functional verification methodology. Per the Press Release: “MediaTek’s complex multimedia designs require thorough verification at the RTL level to confirm interface compliance and the functionality of control logic. MediaTek uses the 0-In Formal Verification technology for bug hunting, which is the process of pinpointing errors during functional verification and analyzing assertions that focus on verification hot spots.”

* Meanwhile, MediaTek announced an agreement “to acquire the assets related to the Analog Devices Othello radio and SoftFone baseband chipset product lines, as well as certain cellular handset baseband support operations, for approximately $350 million in cash. These product lines represented approximately US$230 million in revenue for ADI, based on fiscal year 2006 financial results … The boards of directors of both companies have approved the transaction, which is expected to close near the end of 2007, following the satisfaction of regulatory requirements and other customary closing conditions.”

* Magma Design Automation announced a partnership with UMC to provide “broad physical verification and DFM solution for 65-nanometer designs. The two companies have completed joint qualification of Magma’s Quartz DRC, Quartz LVS and Quartz DFM for UMC’s advanced processes and development of foundry-validated runsets and models that support the flow.”

Ken Liou, Director of UMC’s Design Support Division, is quoted: "The qualification of Quartz DRC, Quartz LVS and Quartz DFM for our 65-nanometer process, and our ongoing collaboration with Magma, demonstrates our commitment to helping our customers address complex SoC design challenges and shorten their time to market.”

* LogicVision announced Silicon Insight, which the company describes as “a new desktop silicon diagnostic solution, [which runs] on a Linux PC or laptop [and] interfaces to a customer's device or performance board through simple USB-to- JTAG cable interface hardware to provide an interactive graphical environment for characterization, debug and diagnosis of silicon devices incorporating LogicVision's embedded test IP. With Silicon Insight it is now possible to perform full device debug and diagnostics without the need to access or tie-up expensive automatic test equipment.” Expect more discussion at ITC in October.

Meanwhile, Adrian Arozqueta, DFT Manager at PLX Technology, offers testimonial: "By using LogicVision's Silicon Insight product, PLX was able to easily characterize an embedded RAM in one of our latest devices. In addition to the advantages in cost and convenience of performing device diagnostics in the lab as opposed to on the production floor, we were able to complete the characterization of the RAM across multiple operating conditions and process corners within hours of the software installation."

* IMEC announced its ultra-low power (0.7 mW), high-speed (50MSamples/s) ADC achieved a figure of merit of 65fJ per conversion step. Per the Press Release: “This is 2.5 times better than the best ADC of this kind ever reported in research papers and an order of magnitude better than the best commercially available ADC IP blocks in 90-nanometer CMOS. The novel IMEC SAR ADC design is especially suited for nomadic applications in the IT realm. Its power scales linearly with the clock rate over a very wide range which makes it very well suited for software-defined radio applications. It is implemented in pure digital CMOS technology, making it very well suited for scaling to the 45-nanometer CMOS node and below. The design is available as 'white box IP' for transfer to the industry.”

* Geensys, a privately owned embedded development tools and software IP company, has been created through the formal merger of two of France’s most innovative and dynamic companies in the embedded market – TNI Software and Ayrton Technology. Per the Press Release: “Geensys will offer a range of embedded development products and services on several levels, focusing on satisfying the embedded development requirements of the automotive, aerospace, defense, railway, industrial automation and telecommunications industries … Drawing on the skills of 245 specialist engineers and the expertise built up in Ayrton Technology since its formation in 2001, Geensys will provide customers with a complete, outsourced embedded product design and realization service covering hardware, software and mechatronic design, product prototyping, product integration, production, test and documentation generation.”

Serge Laverdure, the newly appointed CEO of Geensys, is excited: “We are bringing together the well-proven and highly respected skills, expertise, products and services of TNI-Software and Ayrton Technology to create a powerful new force in the embedded market. Its formation is a classic example of a new, merged company being greater than the sum of its component parts.”

* Fujitsu Ltd. and Denali Software announced their co-development of a DDR DRAM physical interface (DDR PHY) product compatible with the recently announced DDR-PHY Interface (DFI) version 1.0 specification. The companies say the “DDR PHY utilizes the DFI specification, which defines a common interface between the conventional proprietary memory controller logic and DDR PHY designs.”

* Extreme DA announced new corporate headquarters in Silicon Valley. CEO Mustafa Celik is quoted: "To accommodate our growing staff, our new headquarters is five-times larger than our former offices. In just one year, our staff has increased by 100 percent, and we are aggressively recruiting to add more employees to our team by year-end."

* EVE announced that Tensilica used EVE's ZeBu to validate the Diamond 38xVDO Video Engines. Beatrice Fu, Senior VP of Engineering at Tensilica, is quoted: "ZeBu allowed us to validate changing codec and hardware revisions almost immediately. The result was a high confidence that our final product, really a combination of hardware and software, would just work."

* EMA Design Automation and AEi Systems announced version 2.0b of AEi Systems’ Power IC Model Library for the Cadence PSpice simulator. Per the Press Release: “Version 2.0b has over 200 time-domain simulation models for power electronic designs. Several previously unavailable Texas Instruments models debut in version 2.0b, and future updates are anticipated to focus on many of TI’s newest and most popular components.”

* Dongbu HiTek announced a new design library that supports CMOS Image Sensor (CIS) processing at the 110-nanometer node. The company says the new library enables low leakage current in standby status as well as up to 5-megapixel resolution in camera phones.

* Dolphin Integration announced a new release of its SLED hierarchical capture system, which the company says “delivers the long-awaited dual capability for Graphic Entry and Scriptability at once … Compared to current solutions, SLED is both framework independent and open to bridging with EDA tools. It maximizes interoperability at different levels of the design chains.”

* CoWare announced a collaboration with STMicroelectronics to create “an advanced ESL design automation environment based on CoWare's Processor Designer and CORXpert Personalization Kit for STMicroelectronics custom processors.”

Philippe Galliard, Software Tools Development Manager, Software Tools and Services Division at ST, is quoted: "This process is handled securely by the CORXpert software and frees up the engineers so that they can concentrate on optimizing cores rather than being trapped in the manual operation that was previously required. By taking advantage of the shorter development cycles, ST engineers can target the entire application range, from dedicated controls to complex applications in the multi-media domain, with cost, performance, and power optimized custom processors."

* Cadence Design Systems (India) Pvt. Ltd., the Indian subsidiary of Cadence Design Systems, Inc. announced that RFIC Solutions, Inc. “increased productivity two-fold by adopting the Cadence Virtuoso custom design platform … RFIC Solutions successfully completed two tapeouts within the first month of adopting the Cadence technology.”

* Meanwhile, Cadence celebrated the opening of the Cadence Research Laboratory @ Berkeley, which the company says is “just steps from one of the world's most prestigious institutions of higher education and within easy reach of the dynamic economic engine of Silicon Valley.” Multiple high-profile players were on deck for the opening including company President & CEO Mike Fister, Cadence Research Lab Director Andreas Kuehlmann, SIA CEO George Scalise, Berkeley Mayor Tom Bates, U.C. Berkeley Associate Vice Chancellor for Research Robert Price, and reps from the offices of various politicos including Congresswoman Barbara Lee, Congresswoman Anna Eshoo, and Governor Arnold Schwarzenegger. Take that, Stanford!

* Berkeley Design Automation and Matsushita Electric Industrial Co., Ltd. announced a partnership for analog/RF and mixed-signal design verification for Matsushita's Digital-RF Chip Design Platform. Per the Press Release: “The partnership is based on the technology from Berkeley Design Automation's Analog FastSPICE and RF FastSPICE tools.”

* ARC International says it has “extended its leadership in enabling energy efficient SoC design by introducing ‘Energy PRO’ technology that enables ultra low power operation. Configurability enables creation of power efficient cores. Energy PRO further reduces power consumption by as much as four fold. ARC's new Energy PRO technology is supported by hardware and software solutions, and integrated with a new low power EDA flow and libraries that have been specifically optimized to Energy PRO.”

*ARC also announced an Early Access (EA) Program for its new Energy PRO technology that is available to a limited number of OEM and semiconductor companies. The EA Program enables qualified participants to be the first to market with this new industry leading low power technology, which is ideal for applications such as battery-operated mobile devices (WiFi and WiMAX technologies, and digital radios) and implantable medical products (pace makers and hearing aides).

Paul Holt, VP at ARC International, is quoted: "Energy PRO enables the intelligent management of power in an SoC to ensure that each logic or memory component is only using the amount of power needed to perform its function effectively at any moment in time. It includes hardware and software techniques necessary to conserve energy, and allows designers to dynamically take advantage of new power saving capabilities. Applications can use the techniques by directly leveraging the software APIs and code provided by ARC."

* ARC and Cadence Design Systems announced “a new automated Common Power Format (CPF)-enabled low-power reference design methodology (LP-RDM) has been implemented in ARChitect, ARC's patented processor configuration tool. This LP-RDM together with the Cadence Low Power Solution ensures that ARC's new Energy PRO technology is captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction of IP core power.”

*Appro announces support for native Quad-Core AMD Opteron™ 2300 and 8300 Series processors in all of Appro's systems including the HyperBlade cluster series and the XtremeServer and workstation series. Appro servers and cluster solutions based on the new Quad-Core AMD Opteron processor (previously codenamed "Barcelona") are designed to provide high performance, reliability, power efficiency, memory scalability, high bandwidth and low memory latency, delivering a validated optimized Appro solution to meet the demands of multi-core processing for high-performance computing applications.

* Apache Design Solutions announced that MediaTek selected Apache as their EDA partner for addressing 65- and 45-nanometer physical design challenges. The MediaTek-Apache collaboration will focus on areas of power and noise, including power signoff, advanced low power and leakage optimization, reliability methodology, thermal integrity, and IC-package noise management.

Per the Press Release: “Through the MediaTek-Apache partnership, MediaTek plans to establish power and noise signoff flows for their 65/45nm high performance and low power designs based on Apache's advanced technologies, as well as existing products such as RedHawk-EV, RedHawk-ALP, PsiWinder. Sahara-PTE, and Sentinel. In addition, MediaTek and Apache will share their expertise in methodology and signoff for system-on-chip (SoC) silicon integrity.”

* Meanwhile, Apache Design Solutions announced that Toshiba has standardized on Apache's RedHawk for power signoff of their 90- and 65-nanometer designs. Tamotsu Hiwatashi, Senior Manager, System LSI Design Department, System LSI Division at Toshiba, is quoted: "Apache's support has been outstanding, not only in their technical expertise, but also in their responsiveness to meet our needs, which has enabled us to increase confidence in the quality of our designs."

* Altium has donated additional software to the University of Toronto Institute for Aerospace Studies, Space Flight Laboratory (UTIAS/SFL) in support of its CanX satellite missions.
Altium has supplied Altium Designer unified licenses to support the graduate lab's research into novel technologies in space. The company says this graduate training will strengthen the Canadian skills base in space systems engineering, dramatically speed up the development of space systems and lower the cost of space missions.

* Altera announced its Plug & Play Signal Integrity technology, which the company says “redefines FPGA use in high-performance systems by enabling a single card configuration to be plugged into any designated system slot while under system power … [The] technology is an exclusive combination of low-power linear adaptive equalization technology – Altera's new Adaptive Dispersion Compensation Engine (ADCE) – and the hot-socketing capability found in every Altera FPGA. When hot-swapping a single card configuration in a system, the ADCE automatically monitors and adjusts itself for interconnect loss and environmental variations to provide the highest system performance and data reliability available in the industry today.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.