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The thing about an event like the Design Automation Conference is that it doesn’t really matter in what order you attend the events. Each panel, keynote, technical session, workshop, or tutorial is, in fact, a stand-alone presentation offering information and an opportunity to learn. You get to as many as you can, and hope that you’ve guessed right as to which set of events will optimize your experience. Unless, of course, you’re a vendor. Then, as one CEO of a small start-up recently told me, “You’re chained to the booth and attending any sessions whatsoever is out of the question.” That is a definitely a loss. There are great sessions going on all over the place at DAC, so pity the many vendors who were unable to attend any of them.
Following is Part 2 of my DAC Report. Part 1 was published on June 18th.
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The third day in San Diego was the first official day of DAC. The opening session early Tuesday morning was attended by upwards of 600 people gathered in the biggest hall in the Convention Center. Seated at the double row of tables on stage were the 20 members of the DAC Executive Committee in their distinctive yellow shirts. General Chair Steve Levitan welcomed the attendees to the conference and the meeting was off and running.
Before the Best Paper awards, scholarships, IEEE fellows, and lifetime achievement awards were celebrated, however, the session began with presentations in memory of U.C. Berkeley’s Dean of Engineering, Dr. Richard Newton.
Dr. Alberto Sangiovanni-Vincentelli stood mid-stage and admitted that talking about his lifelong friend and colleague was a painful and difficult task. Nonetheless, he spoke in detail about Newton’s work, his creativity and his drive, and their dynamic technology partnership. Alberto ended with a poignant: “Goodbye, Richard, my friend.”
A quote from Newton’s 1995 DAC keynote flashed across the screen: “If there is a single point I wish to make here today, it is that as a discipline, both in industry and in academia, we are just not taking enough risks today, and most certainly not from a technical perspective.”
Dr. Newton’s wife, Petra Michel, spoke next from the stage about their lives together, of their children and, in particular, of Dr. Newton’s work to improve the role of women at U.C. Berkeley and in the world.
Finally, Dr. Ellen Sentovich spoke about the Dean Richard Newton Memorial Professorship in Synthetic Biology that has been established at Cal based on a generous outpouring of funds from the industry. The first 30 minutes of DAC were emotional ones – and that tone continued on through the various awards and accolades for members of the industry who have contributed in every way to progress in the technology.
When it came time for the keynote address, Dr. Oh-Hyun Kwon, President of the System LSI Division at Samsung, took the podium and delivered a lengthy address complete with detailed statistics and slides – mandatory props given his huge topic: “A Perspective on the Future Semiconductor Industry: Challenges & Solutions.”
Unfortunately, those of us sitting in the first several rows could not hear him at all because of the acoustics in the hall, so I took my laptop and moved to the very back of the room. I sat on the floor and watched Dr. Kwon’s talk on the big screens and then could hear quite nicely. [The talk was taped and it would be time well spent to go listen to it online if you couldn’t be there.]
Above and beyond the staggering figures – 7.8 billion wafers currently rolling out of the fabs, with estimates of 15 billion wafers by 2015 – Kwon noted that only 100 products this year will actually enjoy a production run of over 100 million units: “The costs are therefore difficult to amortize over the lifetime of the product.”
Kwon acknowledged the global tech alliances required to push the next node into reality, whether it be 65, 45, or 30 nanometers: “The semiconductor market will continue to grow to new applications and higher performance demands. Huge capital expenditures will necessitate consolidation within the industry, and will increase the important of collaboration between key players in order to maximize ROI. Strategic alliances and standardization of both equipment and IP are going to be critical.”
Kwon ended his address with a stopgap solution to address today’s out-of-control design complexities. Forget SoCs where everything’s packaged onto one highly integrated (impossible to verify) chip. Instead go with: “Many-core designs and chip/package/board co-design!”
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One of the highlights of my days at DAC took place immediately after the Tuesday morning plenary session, while dignitaries, honorees, keynote speakers, DAC Executive Committee members, etc., were milling around below the stage before rushing to their next appointment. I spoke at length in the emptying ballroom with U.C. Berkeley’s Jan Rabaey and IMEC’s Georges Gielen about the future of electronic design automation – initiatives that are nudging the industry towards system-level design and nanotechnologies, including carbon-based nano-scale systems.
Ours was a wide-ranging conversation that ended with a debate as to the optimal order of academic training, if it is to include electrical engineering, computer science, and biology. The debate was based on the premise that biological systems are offering some of the most compelling ‘adjacencies’ with which to expand on applications of the knowledge base already established in design automation. My thesis was that biological systems are built on first principles in physics, chemistry, and self-replicating systems and, therefore, must be studied before ‘man-made’ disciplines such as engineering and computer science.
Gielen and Rabaey disagreed with me completely. Their assertion was that engineering and computer science are tantamount to ‘first principles’ when it comes to design automation. When it comes to creating and/or controlling carbon-based systems, optimizing design is the desired destination, not biological systems in themselves. Therefore, the disciplines of engineering and computer science must lead the curriculum, followed only then by formal introductions to biology and carbon-based structures.
The arguments on the Gielen/Rabaey side of the debate were compelling, but I was not totally convinced. I was convinced, however, that the greatest moment at DAC 2007 – especially for those truly interested in the future of EDA – was going to be taking place during Rabaey’s lunchtime keynote address on Thursday, June 7th. Unfortunately, I was slated to leave San Diego by end-of-day on Wednesday and was not going to be able to hear Rabaey’s address. The wise folks on the DAC Executive committee have posted Jan’s talk on the DAC website, however, and we can all go hear it now: “Design without Borders: A Tribute to the Legacy of A. Richard Newton.”
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Late Tuesday morning, one of the most highly anticipated panels of the conference took place in Room 6C, “Mega Trends and EDA 2017.” Presenters included Argon Capital’s Jean Antonio Carballo, Synopsys’ Aart de Geus, TSMC’s Fu-Chieh Hsu, U.C. Berkeley’s Kurt Keutzser, and NEC’s Kazu Yamada. Given my usual scheduling conflicts, I was only able to sit in on Keutzer’s presentation.
Keutzer was happy to report that he published an article 6 years ago in EE Times that accurately predicted “Programmable Platforms will Rule.” Now Keutzer’s got a new prediction, and you probably won’t have to wait another 6 years to wait to see if he’s correct. Prof. Keutzer is predicting that the industry is in the process of abandoning its obsession with Moore’s Law, and is moving instead to a full and complete obsession with many-core processors. Briefly glancing through the amount of content in the DAC program that touched in one way or another on multi-core, multi-processor, multi-thread, multi-multi, and mega-multi, I’m predicting Keutzer is correct. In fact, his 2007 predictions for 2017 are probably already here.
Meanwhile, although I wasn’t there for the whole session, Room 6C was clearly standing room only from 10:30 to noon. The electricity in the room was tangible and surely many of the 300+ people squished into the too-small room attended the 90-minute session in its entirety. Surely, also, this session was a helluva lot more interesting and candid that the legacy session it replaced – the annual CEO panel that used to be the anchor tenant of late Tuesday mornings at DAC. The guys on this year’s Mega Trends panel seemed to be throwing ideas out there, and tossing them around, in a way that simply wasn’t possible in those CEO panels of the past. Good job to everybody involved in setting this one up!
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I rushed from Room 6C to Room 33A-C to moderate a noontime panel at the annual ESL Symposium, sponsored this year by Mentor Graphics. Upwards of 300 people showed up to enjoy a (free) box lunch and two hours of (eventually) lively discourse between the panelists, including Mentor Graphics’ Simon Bloch, CoWare’s Eshel Haritan, Samsung’s Joonhwan Yi, STMicro’s Laurent Ducousso, and ARM’s John Goodenough – 2 ESL providers, 2 ESL users, and one IP guy. As moderator, it was difficult to take a compete set of notes, but I will tell you that my take-aways from the panel included the following:
* The industry is (slowly) moving towards a definition of ESL, but it remains a truth (for some) that “system level” is always one level above the level of work you’re working on – and, therefore, varies from constituency to constituency.
* Over-simplifying the definition, and challenges, of ESL is dangerous, and distinctly counter-productive to progress in the technologies associated with moving up levels of abstraction.
* There are many vendors who describe themselves as ESL vendors, but not all of them actually qualify to carry the moniker.
* There is debate among those who legitimately position themselves as ESL tools providers as to which company currently enjoys primacy. I was reprimanded for introducing Mentor Graphics as the industry leader. Yes, they paid for lunch for hundreds of people, but CoWare might in fact be perceived as industry leader.
* IP vendors would like more sophisticated ESL tools in order to enhance the process of “stitching together” blocks of IP, to ease the challenges of reconfiguring IP for new reuse targets, and to assist in creating IP products in the first place.
* System integrators and semiconductor folks would like more sophisticated ESL tools because their projects and designs are growing more complex by the day, hour, and minute. They’d like to see tools to assist in partitioning the design, verifying the design, and implementing the design. (Who wouldn’t?)
* ESL tools are needed to reduce the costs of ECOs, to enhance the caliber of the models desperately needed for design and integration, and to ease the verification bottlenecks facing the industry.
* Big EDA vendors have enormous obligations to legacy customers, and legacy tools, and therefore face huge (but not insurmountable) challenges in expanding their offerings to include higher levels of abstractions.
* As has been true for a number of years, it sure would be great if there was a seamless, automated flow all the way from the system level down to RTL, and beyond.
* Organizations like SPIRIT and OSCI are helping to push legitimate solutions to multiple parts of the “puzzle” of making ESL a reality.
* ESL is happening even as we speak – it’s moved beyond the “evangelism stage” – but its potential is not fully realized, as yet.
* A signpost of progress will be, among other things, a reduction of “ESL flows” from today’s 20-or-more flows, to just 3-or-so widely accepted/standardized flows.
* When ESL breaks out of its “digital design” straightjacket and expands to fully embrace hardware/software design, growth in the technology will be explosive.
* Stay tuned for many more chapters in the ESL story.
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From ESL, I rushed over to DFM and a session entitled “Making Manufacturing Work for You.” In truth, I was starting to suffer from DAC-data overload at that point, but noted the following paraphrased comments from the session:
Virage Logic’s Yervant Zorian – We need an integrated solution between internal test and post-manufacturing test equipment.
Synopsys’ Greg Yeric – The ecosystem required to answer today’s manufacturing challenges is complex and must include tools for yield data management, yield consulting, and attention to the physics of the situation. The quandary over IDMs versus the fabless/foundry model remains, but great EDA companies like Synopsys are offering solutions that rise above those concerns.
Chartered Semiconductor’s Walter Ng – It’s important to get chip data off of the wafer quickly so that an initial design can get to volume yield as quickly as possible.
Anonymous – DFM is not a simple problem. It’s a complex issue, which requires complex DFT solutions. Amen.
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From DFM, I went to WACI – the first annual DAC Wild & Crazy Ideas session. There was some darn great stuff being thrown around during this 2-hours session. Multi-processor generators, Precision Timing Machines, Quantum-like Networks on Chip, Cryptography (“Design Automation is emerging as an enabler of new types of system security.”), and DAC’s own 2007 General Chair Steve Levitan talking about nano-scale technology and distributing data from point to point across random graphs on grids.
All told, the WACI session was a highly attended session with lots of dynamic energy in the room. Congrats to the DAC Executive Committee for having the guts to put this session on the program. My only comment: Get even WACI’er, if you do it again! It’s not a waste of people’s time to hear about zany ideas that are really a long way from being commercialized.
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Instead, I ran off to the Magma Design Automation Press & Analysts Dinner being held in the House of Blues nearby to the Convention Center – an odd choice of locale, given the new lease on life that’s currently infusing the whole Magma story. What with the recent cessation of legal wrangling with Synopsys, CEO Rajeev Madhavan was clearly elated to be laying out a complex technology and business roadmap for the company to his well-fed audience. No Blues to be heard in any of it!
The last stop on the Tuesday DAC Train was, of course, the Denali Sock Hop, back by popular demand in its 2004 venue at the On Broadway Club in downtown San Diego, and luckily right around the corner from the House of Blues.
The Denali Party was a zoo – people, food, open bar, thousands of EDA folks ready to unwind with the noise (and music) provided by the usual EDA suspects including, The Full Disclosure Blues and the Chad Tuckers. The centerpiece of the 2007 party was, however, (the First Annual?) EDA Idol contest, with judges Dennis Brophy, Karen Bartelson, and Simon Davidmann. (Who doesn’t know these folks work for Mentor, Synopsys, and Imperas, respectively?)
A picture’s worth a thousand words, and the photo nearby says it all. The party and the contest were wild.
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Wednesday morning, noon, and night …
Wednesday, June 6th, was my last day in San Diego. I was running out of steam, out of attention span, and growing sick of running on caffeine. However, I didn’t have to moderate any panels on Wednesday, so it was the one day at DAC I was honestly looking forward to. And, surprisingly enough, the best part of the day was the 10 minutes I spent at Starbucks in the Convention Center. I got into a deep, albeit too-short, conversation with an EDA executive who let me in on a big secret about DAC, and EDA.
Per the exec, the convention was somewhat under attended this year for one solid reason. The semiconductor guys in Asia were not there in great numbers, or at least not compared to previous years. And that’s because the semiconductor guys in Asia are struggling with both business issues and design issues, and the two issues are linked. Again per this exec, the EDA vendors are not stepping up to help their customers in Asia as effectively as they might because the EDA vendors continue to maintain that they can and should be calling the shots as far as which tools to develop, and which markets to pursue. It seemed a confusing picture. Why would the EDA vendors not be fully tuned to what their customers need and want? I don’t know. Do you?
Meanwhile, Wednesday was Auto Day at DAC. I went to two Pavilion Panels and a technical session/panel discussion, and learned the same thing several times over. Cars are cool, cars are everywhere, and cars are all about Semiconductors on Board. In fact, cars are just mobile platforms, so move over Detroit because cars are no longer about drive trains They’re about embedded systems and the only question that remains is: How soon will drivers catch on, sit back, and leave the driving to the systems on board?
I actually learned one other thing about cars on DAC Wednesday. I learned that Carnegie Mellon seems to have the lion’s share of the funding when it comes to academia partnering with industry and/or government to pursue advanced research. Perhaps not a fair conclusion, and I’m sure many universities would protest, but CMU was everywhere on Auto Day at DAC on Wednesday.
At lunchtime on Wednesday, I attended a large meeting of IPL – stands for Interoperable PCell Libraries – an alliance of EDA companies who are collaborating to “create and promote” standards for open-source interoperable PCell libraries that support the OpenAccess database from Si2. The companies include AWR, Ciranova, Silicon Canvas, Silicon Navigator, Synopsys, Magma, and Virage Logic.
So far, they’ve produced “a high-quality proof-of-concept library using a generic 0.13 micron process [which] demonstrates that the IPL mechanism works.” Sigh.
This is a really big, complex, and contentious issue and you can bet you’ll be hearing lots more about in the coming months (and years). The take-away I gleaned from my visit to the luncheon? “You can have PCells with no SKIL required.” That’s a pun. If you don’t get it, go to the IPL website and see if you can figure it out.
Over the course of Wednesday at DAC, I also met with executives from various companies including Denali, VaST, IC Manage, Algotronix, SynCira, CoWare, VeriEZ Solutions, and Synopsys.
In truth, I found all of these conversations to be enriching. The executives and folks who are at the helm of the EDA companies, big and small, are fascinating folks. They are criticized for so many things – for being marketeers, for attempting to control the market, for putting spin on bad news, or worse, putting spin on good news, for overstating their worth, financial or otherwise, and, of course, for producing imperfect tools. But at the end of the day, the buck stops with these guys. And so does my DAC report.
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As I flew out of San Diego Wednesday evening and glanced back at a city aglow in the setting sun, it was hard not to contemplate the leadership in the industry. It’s no secret that the executives of all of the EDA companies are, appropriately and constantly, looking down at their bottom line and over their shoulders to their investors, stockholders, and Boards of Directors. An EDA executive’s life is full of stress and concerns – everything from keeping the lights on to deciding, yet again, whether or not to buy into a booth at DAC next year. These are tough decisions and never easy. Sure, it’s simple enough for me to say, “Of course you should be coming back to DAC!” But that answer may not be so clear to these managers.
So let me put it a different way. If electronic design automation is tough and needs constant innovation, and if innovation is about interacting with customers, competing and/or partnering with other vendors, hearing from and/or funding academics and their students, and being part of an industry-wide conversation – where better to do all of this than at a conference where all of the parties involved are in attendance?
From my perspective that conference looks like the Design Automation Conference. And from multiple conversations I was privy to in San Diego, I think many would agree with me. But only time will tell.
The sun has set on the 44th DAC in San Diego, but preparations are already underway for the 45th DAC, scheduled for next year in June. For now, I look forward to seeing all of you in Anaheim in 2008 and hope you all will be there as the beat goes on in EDA. The story of this industry, and this conference, is a great one – albeit complex and often difficult to decipher – and I believe there are many more chapters to be told before it comes to an end.
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In the weeks after DAC …
Although the industry usually issues a joint sigh of exhaustion after DAC, the news continues to come pouring out of the companies (see below). These last several weeks, Cadence has been particularly active with announcements of various technology initiatives and/or releases including tools for system-in-package design, and tools to bring physical design data upstream to the logic designers in a more painless/appealing way. Cadence capped off recent news items by acquiring a company in the DFM space, Invarium, an enterprise that provides tools for lithography modeling and so forth.
Meanwhile – speaking alphabetically – Agilent (wireless library update), Altera (embedded processor), Ansoft (EMF simulator), CAST (JPEG encoder core), Ciranova (PCell authoring tool), eSilicon (peripheral subsystem architecture), Interra (VHDL front-end), Nascentric (multi-thread simulator), and Novas (unified debug roadmap) also all made interesting technology announcements in recent weeks. Don’t any of these people know how to spell S-u-m-m-e-r V-a-c-a-t-i-o-n?
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Call for papers …
Ansoft Corp. announced its First-Pass System Success application workshops, taking place September 12th through November 15th in Asia, North America and Europe. Papers can be submitted up to August 31, 2007 via the company’s website, and should address such topics as IC design and verification, signal and power integrity simulation, RF, microwave and antenna design, and packaging and PCB design.
DATE 2007 is calling for papers in the areas of design methods, tools, algorithms and languages, design, test methods and tools, and embedded systems software. The deadline is September 9, 2007 for the March 2008 conference in Munch (March 10-14).
ISQED 2007 is calling for papers, as well, in the areas of manufacturing processes and devices, design, and EDA tools. The deadline is September 30, 2007 for the March 2008 conference in San Jose (March 17-19).
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Off the wires …
Acacia Research Corp announced that its Disc Link Corp. subsidiary has signed a license agreement with Altera Corp. covering patents relating to portable storage devices with links.
Agilent Technologies announced an update to the Agilent 3GPP LTE Wireless Library, which the company says “works within the ADS environment using the Agilent Ptolemy simulator to streamline the design and verification process. The library provides preconfigured simulation setups with signal sources for downlink and uplink, along with transmitter analyses such as spectrum, complementary cumulative distribution function (CCDF) and waveform measurements.”
Altera Corp. and eCosCentric Ltd. announced the eCosPro RTOS for Altera's Nios II embedded processor, the world's most versatile soft-core processor. Per the Press Release: “Altera Nios II processor customers now have access to a complete eCosPro solution consisting of the run-time system, complementary host tools, and certified third-party applications. eCosCentric will also develop, maintain and make available to Altera customers, its eCosPro Starter and Developer's Kits for the Nios II processor.”
Ansoft Corp. announced a “strategic partnership” with ZTE Corp. The companies say that ZTE engineers are using Ansoft’s signal and power integrity analysis software to predict radiated emissions and induced interference from PCBs and examine multiple PCBs within a cabinet to determine trends in system-level emissions.
Ansoft also announced its SIwave v3.5 full-wave electromagnetic field simulator, which the company says is optimized for signal-integrity, power-integrity, and electromagnetic interference (EMI) analysis of high-speed PCBs and IC packages. The company says this release includes: “a fast finite-element-based DC solver optimized for extraction of power rail geometry in complex low-voltage/high-current PCB and package designs, [and] access to voltage drop and current flow information through all layout elements (vias, bond wires, sources, resistors, inductors, etc.) in tabular format.”
ARTiSAN Software Tools announced that BAE Systems Integrated System Technologies is using ARTiSAN Studio for implementation of its OMG SysML-based systems engineering processes.
Atrenta announced that Patrizia Owen has been named CFO. Owen has 15 years’ experience working for pre-IPO and early-stage companies. Previously, she has served as CFO at DigitalPersona, inOvate Communications Group, and Beatnik, Inc. She has also worked in various capacities at I/Pro, Engage, CMGI, Compression Labs, VTel, Amgen and HP. Her experience spans multiple mergers, acquisitions, and IPOs. Owen has an MBA from the University of British Columbia and a BA in Economics from the University of Western Ontario.
Cadence Design Systems announced it has acquired Invarium, a San Jose-based developer of advanced lithography-modeling and pattern-synthesis technology. The companies say that Invarium's expertise is in “the development of pattern-synthesis technologies that enable superior photomask design and process optimization, encompassing the entire manufacturing-process flow from mask making to lithography and etch … Invarium's pattern synthesis capabilities enable superior pattern resolution and faster yield ramp for designs targeted to 45-nanometer-and-below process technologies.”
Cadence Design Systems announced that Cadence SiP (system-in-package) technology is now integrated with the company’s Virtuoso and Encounter products. Per the Press Release: “Cadence [now] enables designers to converge diverse IC and package-assembly technologies into highly integrated products … [Cadence SiP] supports the new OpenAccess-based Virtuoso platform for an RF-module design and circuit-simulation-based flow. It integrates a new post-layout parasitic extraction and back annotation flow into automatically maintained circuit-simulation test benches.”
The news was endorsed by STMicroelectronics, and includes these additional details: “The new SiP digital flow includes logical co-design connectivity and authoring support, as part of the System Connectivity Manager. This isolates the front-end designer from physical-only changes, such as pin swap association ... Other enhancements to this release, for both the RF and digital flows, include autobond for rapid wirebond padring evaluation, object-action and action-object use models, improved SI model-extraction accuracy for designs without reference planes, 3D die stack object swapping, extended manufacturing signoff rules, and capabilities for manufacturing accurate wirebond profiles and parasitic models.”
Cadence announced, as well, that Ikanos Communications is using the Incisive Palladium accelerator/emulator series for system-level verification needs.
Cadence also announced an “advanced design flow to improve manufacturability and yield for 65 nanometer designs” has been developed by STARC, based on Cadence products. The organizations say they have been collaborating for 15+ months to provide STARC member companies with these new DFM capabilities.
Finally, Cadence has been very busy because it has also announced its Logic Design Team Solution, which the Press Release says, “offers a new design with physical approach that [automatically delivers] an accurate physical description of the design into the logic design stage … Logic design teams now can automatically design and synthesize with real physical floorplan data, virtually eliminating disparities between logical and physical timing views … The Cadence Logic Design Team Solution [replaces] traditional statistical wireload models with real physical timing information. The RTL-to-gate transformation and optimization process is driven by a proprietary Physical Layout Estimation (PLE) algorithm in [Cadence’s] Encounter RTL Compiler … [Then, Cadence’s] First Encounter silicon virtual prototyping capability is incorporated into the synthesis cockpit to quickly obtain the most accurate view of physical interconnect timing. The combination of physical layout estimation algorithms and embedded silicon virtual prototyping technologies creates a comprehensive interconnect modeling strategy that spans from RTL-to-gate level and accurately models both long and short wires, [eliminating] disparities between logical and physical timing views, virtually eradicating schedule-killing, big-loop iterations and the need to over-margin timing at the cost of power.”
CAST, Inc. announced a new version of its JPEG 2000 encoder core. The JPEGK2-E core was developed by CAST partner, Alma Technologies, and per the Press Release, is “faster, requires no external processing, adds significant features, and is customizable and highly scalable … [This] new version provides high-quality compression of still or video images using the JPEG 2000 standard (ISO/IEC 15444-1) … [It] improves processing and makes it significantly easier to integrate JPEG 2000 in ASIC- or FPGA-based systems. [It includes]: nearly twice the processing speed of the previous version, with some of the fastest processing rates available – over 100 MSamples/sec for FPGAs and over 200 MSamples/sec for ASICs; a new rate control capability, by which image quality is maximized while maintaining a constant post-compression bit rate that satisfies a system’s transmission and decoding requirements; expanded support for arbitrary large images, now handling frame sizes up to 4096 by 4096 pixels without tiling; and full hardware handling of both Tier-1 and Tier-2 JPEG 2000 encoding, eliminating the need to do Tier-2 encoding in software running on an additional processor.”
Ciranova announced version 4.1 of its PyCell Studio is now available on multiple platforms, including Microsoft Windows. Per the Press Release: “For the first time, developers will be able to author PCells using Windows-based environments, and then deploy them on another platform, such as Linux or Solaris. A single PyCell library will work on any platform, regardless of which platform was used to create it.”
CMC Microsystems announced Ian McWalter is the new President and CEO. McWalter has 30+ years’ experience in the semiconductor and electronics industries, and 15 years’ experience on the CMC Board of Directors where he served as Chairman from 1993 to 2005. Previously, he has served as CEO of Toumaz Technology and President/CEO of Gennum Corp. McWalter also held management positions with Bell Northern Research (now Nortel Networks). He has a PhD in EE and a BSc in physics from the Imperial College of Science and Technology in London.
Denali Software announced that Beceem Communications incorporated Denali’s Databahn DDR memory controller into Beceem’s “first commercially available terminal chipset for the latest Mobile WiMAX standard.” The companies say that “Databahn DDR controller IP enabled Beceem engineers to achieve optimal system-level performance for its DRAM systems in the design of the 802.16-2005 mobile wireless BCS200 chipset.”
edacentrum announced it’s edaTrend 2007 Conference Reports, covering both DATE 2007 and DAC 2007. Per the Press Release: “edacentrum’s ‘edaTrend’ reports focus on essential industry, technology and business trends highlighted and discussed in conference keynote addresses, panel discussions, and some special sessions, as well as issues raised on the exhibition floor. They also contain source and reference information, and a short written evaluation with ratings for each session.” The reports cost 250 euros, plus tax, and comes in a paperback version perfect for reading on the beach or a PDF version more suitable for the office over coffee and a doughnut.
eSilicon Corp. announced a new ARM processor-based peripheral subsystem architecture. Per the Press Release: “The new subsystem reduces time-to-market for ARM Powered SoC solutions by providing developers with several industry-proven, off-the-shelf system technologies, enabling them to focus on their application-specific, value-added functions.”
Interra Systems announced “the integration and introduction” of Jaguar as a VHDL front-end to several products from OneSpin Solutions, including OneSpin’s 360 Module Verifier and 360 EC Equivalence Checkers. Peter Feist, President and CEO of OneSpin, is quoted: "We provide advanced formal verification solutions that put very specific requirements on the front-end technology … Interra's portfolio of front-end technology and Beacon test-suites for recent EDA standards, such as System Verilog RTL, SVA and PSL, and their very responsive support, saves us development time and ensures full compliance to the standards.”
Jetway Security Micro, a security products company based in China, and Elliptic, recently ranked as the fastest growing supplier of security semiconductor IP by Gartner Research, have signed a license agreement for Elliptic's asymmetric security engines.
Per the Press Release: “The license will permit Jetway to better serve the emerging Asian and world markets for security systems requiring high performance public key algorithms. The two companies have also agreed to collaborate on a long-term basis to tailor the engines to the evolving needs of the target markets and applications specified by Jetway. Jetway Security Micro is a subsidiary of Jetway Security Information Company Ltd. which has been in business for 20 years with offices in Wuhan, Beijing and Shanghai China. The company has shipped security solutions for government and commercial applications in China and is now in an aggressive growth phase to capture more business, not only within China but also in export markets around the world.” An interesting story.
Kilopass Technology announced a collaboration with TSMC to develop Kilopass’ XPM NVM one-time programmable IP. The companies say XPM has been qualified on TSMC’s 0.13-micron CMOS logic process technology.
MOSIS announced availability of IBM’s 0.25 micron SiGe BiCMOS 6WL technology. The companies say the process is particularly well suited to “high-performance analog chip design for consumer wireless applications, has 5 metal layers, and supports metal-insulator-metal capacitors … Design kits that encompass IBM’s design rules, process specs, SPICE parameters, and cell libraries are available.”
Nascentric announced AuSIM MT, which the company describes as a multithreaded version of its simulator, under development for almost 2 years and based on 10 patents – 5 granted and 5 pending. Per the Press Release: “AuSIM MT was built from the ground up to automatically handle the partitioning and execution of the simulation across multiple processors … Nascentric supports the product for both AMD and Intel multi-core architectures.”
Novas Software announced the company’s roadmap for “the continuing evolution of its debug automation platform for large digital ICs and SoCs. The Novas platform unifies the languages, abstractions, and tools needed to cut in half the time it takes to understand and debug design behavior starting from system-level specification through silicon implementation. Novas' latest advancements are expected to deliver three-to-ten times more performance and capacity across the entire platform, and fuel adoption of SystemVerilog-driven verification methodologies with more automated debug solutions.”
“Performance initiatives are focused on enabling fast, fine-grained access to critical portions of big designs and new incremental, on-demand approaches that accelerate automated analysis and tracing capabilities. Novas is also building on its comprehensive SystemVerilog infrastructure with enhanced SystemVerilog Assertion (SVA) debug solutions and source code debug support for SystemVerilog Testbench (SVTB) descriptions. These capabilities are being rolled out with quarterly releases of Novas' Verdi Automated Debug System starting this month.”
OCP-IP (The Open Core Protocol International Partnership) announced support of Cadence's Assertion Based Verification IP (ABVIP) for the development and verification of the OCP protocol. Per the Press Release: “Cadence's ABVIP is used for interface monitoring in simulation, as well as exhaustive formal analysis of OCP implementation including compliance. OCP-IP is taking important steps to alleviate these design challenges by supporting the ABVIP from Cadence.” Good news.
Optimal Corp. announced IC package thermal analysis for TSMC's Reference Flow 8.0, which is targeted at 45-nanometer designs and includes statistical timing analysis for intra-die variation, automated DFM hot-spot fixing, and new dynamic low-power design methodologies.
Samsung Electronics announced that “over the past year” it has introduced 6+ technological advancements that extend battery life in notebooks, MP3 players, digital cameras, video camcorders, multimedia phones and cellular handsets. Per the Press Release: “These design improvements are part of a concentrated effort by the company to move to more energy-efficient chip and display designs, utilizing nano-scale technology breakthroughs, new sensor technology and advanced manufacturing techniques.” Undoubtedly their pals in EDA had a hand in all of this success.
Silicon Canvas announced that PixArt Imaging selected Silicon Canvas’ Laker L3 as the standard full custom layout tool for its image sensor IC designs, and image-processing algorithm IC designs. Per the Press Release: “The selection of Laker represents an important milestone in PixArt's on-going efforts to improve overall design productivity.”
SoftJin announced that Blaze DFM is now a customer. The companies say that SoftJin tools used by Blaze include the Bi-directional OpenAccess to OASIS Translator and custom verification package for validation of software modules in Blaze's products.
SynaptiCAD released version 12 of its WaveFormer Pro and DataSheet Pro timing diagram editing and waveform translation products. The company says the new version includes 12+ new features, including an improved “timing analysis engine, timing diagram documentation capabilities, and waveform translation support.”
Synopsys announced Teradici Corp. achieved “first-time silicon success utilizing Synopsys' Galaxy Design Platform products, Discovery Verification Platform products, DesignWare IP, and Synopsys Professional Services on their first multi-million-gate SoC.” Also good news.
Tektronix announced it is using Sequence Design products in the Tektronix design flow and has “reduced design closure times by preventing time-consuming iterations between separate timing, SI, power analysis and optimization tools.” Good news, as well.
Virtutech announced that IBM used Virtutech’s Simics across a team of hundreds of developers to speed the development lifecycle of IBM’s POWER6 platform.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.