October 14, 2002
Apache Unveils Next-Generation Power Integrity SOC Tool
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| by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!
Apache Design Solutions released Tomahawk-S, a next-generation power integrity solution for voltage drop, electromigration, and power analysis of current and future SoCs. SoC designers can run multiple iterations in a single day on massively hierarchical designs using the tool, saving weeks when compared to traditional methods, Apache asserted. The company claims that the tool's performance, accuracy and ease-of-use is what enables the tool to convergence on an optimized physical power grid early in design.
Tomahawk is driven by a single-kernel architecture that supports power analysis, network extraction, reduction, and simulation, providing orders of magnitude in speed improvement over existing multi-kernel approaches, the company said. Based on extensive customer benchmarking, Tomahawk-S processes over four million gates in 10 minutes, leading to runtimes of less than one hour for large 25 million gate designs. Tomahawk's embedded one-step hierarchical database promises to eliminate the inaccuracies associated with traditional “black-boxing” or the “block-by-block” abstraction approaches of handling designs with different levels of abstraction. Apache said Tomahawk-S
is the first product in its lineup of physical design integrity analysis and simulation tools for power, timing and system I/O.
In other product news, Emulation and Verification Engineering (EVE), SA integrated ZeBu, its emulation platform, with SystemC, the leading C-based design language. The integration was demonstrated in the Xilinx Booth, at the recent SAME (Sophia Antipolis forum on Micro-Electronics).
The company's president and CEO Luc Burgun, believes that since SystemC appears to be the de-facto leader in the C-based design language war, SystemC's customers have now a compelling reason to adopt this design validation technology as they will be able to speed up the verification cycle by several orders of magnitude compared to existing technologies, and still enjoy full visibility into the design at run-time.
Built on a PCI board, ZeBu ZV-6000 introduces a breakthrough and proprietary interface, called Reconfigurable Test Bench (RTB) that connects the design-under-test to the test environment providing for exceptional throughput. The design-under-test is emulated via two Virtex II XC2V6000 devices, augmented by 128 MBit of SRAM memory, which collectively support a design capacity of more than one million ASIC gates. Through the RTB, SystemC models co-simulate at the signal-level through SystemC communication port reaching 70K cycles per second. Whereas, SystemC models co-simulate at the transaction-level through the channel communication class at several million of cycles per second, a
performance never claimed by any emulator or accelerator. Further, the revolutionary RTB allows access to any internal signals of the design-under-test without compiling the internal probes, EVE said.
Synchronicity, Inc. and Summit Design integrated the Synchronicity Developer Suite design collaboration and management solution with Summit's Visual Elite. Together, the tools allow ASIC and FPGA developers to collaborate on design definition and verification, even across multiple sites, while supplying the information project managers need to ensure project success.
The integrated tools are currently in use at MBDA France to develop system-chips combining unique and high-value functional blocks. MBDA's design teams use Visual Elite to specify, simulate and debug designs, while using DesignSync to manage design data from the beginning of the design process through to physical implementation in its geographically dispersed locations. Consistent data views are available to all designers, regardless of their location.
Additionally, the companies have integrated the design management tools found in the Developer Suite, DesignSync, into the Visual Elite user interface. Visual Elite provides IC and system designers with a comprehensive environment to capture design concepts graphically and textually to verify design behavior. DesignSync makes design data available to the entire project team, no matter where they are located. The other component of the Developer Suite, ProjectSync, enables multi-site project tracking, communications and collaboration.
More news from Summit Design: The company began shipping Visual Elite 3.0 to customers, right on time. The new version, that was announced just before DAC 2002 supports System C 2.0, VHDL, and Verilog. It is being shipped with FASTC, Summit's high-performance RTL 'C'-based design language, as well. FASTC targets RTL design to accelerate simulation performance over conventional HDL and 'C' event-driven engines. FASTC blocks are integrated with other C/C++ and HDL blocks at any abstraction level and can be automatically mapped into synthesizable HDL code.
CoWare Inc. and Denali Software Inc. announced an integrated platform for simulating memory and optimizing memory system performance for SoC designs. Denali's MMAV verification intellectual property (IP) software is now integrated with the CoWare N2C system-level design environment. By using Denali MMAV memory models in the CoWare N2C methodology, designers have access to robust simulation models for virtually any commercial memory device.
During simulation, the models provide valuable performance metrics for the memory system, and automatically test for potential design bugs at the memory interface. The C-based models from Denali are integrated directly with CoWare N2C, providing a seamless simulation and verification environment for advanced SoC development.
Alan Naumann, president and CEO of CoWare, has agreed to represent the Electronic Design Automation (EDA) Consortium on the Design Automation Conference (DAC) Strategic Committee. The committee defines the future direction of the 40-year old conference. In this role, Naumann will attend committee meetings and advise the committee on the EDA Consortium's position on DAC's future direction. Naumann was elected to a two-year term on the 12-member EDA Consortium Board of Directors in April 2002.
Jon Turino, known for his expertise in ATE and DFT/BIST, announced the immediate availability of consulting services in the areas of product design for test strategy, ATE and BIST marketing strategy development, market studies and customer surveys, and a host of collateral services including brochure, data sheet and press release development.
“By taking advantage of out-sourced project or per diem based consulting companies can begin or complete projects that have been put on hold, or reluctantly abandoned, due to the massive reductions in fixed salary costs that have occurred over the least year in the semiconductor equipment and related businesses,” Turino explained. “The increasing shift from functional (or performance) test strategies to structural (or defect-oriented) methods, particularly at wafer probe and burn-in, has created new opportunities for SoC and ASIC designers to contribute to lower test costs throughout the semiconductor manufacturing process. It is also presenting opportunities for both
existing and new ATE vendors to introduce low cost IC engineering validation and production test systems for DFT and BIST enabled designs. Thus IC design and test teams may need help in arriving at the most cost effective DFT and BIST implementations. And ATE and BIST IP vendors supporting such strategies may benefit from outside help in getting their messages across.”
Services range from DFT/BIST implementation consulting to article, application note and white paper development. E-Mail:
InnoLogic Systems, Inc. appointed Yukari Chin to senior director of marketing. In this position, Chin will be responsible for establishing and directing the company's strategic initiatives, and increasing the market awareness for InnoLogic's products. Chin brings over 13 years of EDA industry experience in marketing management and applications engineering. Prior to joining InnoLogic, Chin served as director of marketing for Axis Systems, Inc., where she was responsible for developing corporate positioning and communications strategy for the company and its products as well as product management of new verification products. Earlier, she was a product marketing manager
for various products at Synopsys, Inc. and served in marketing and applications engineering management roles at IKOS Systems, Inc. (now Mentor Graphics). Chin began her career as an ASIC designer at Hughes Aircraft. She holds a Bachelor of Science degree in Electrical Engineering from Oregon State University.
Inovys Corporation has partnered with Q-star Test of Belgium to develop advanced IDDQ test capability for its Ocelot DFT Test System. Q-star Test NV will provide advanced quiescent-current measurement technology; custom integrated modules, and related intellectual property. Inovys will integrate these modules into its Ocelot DFT Test System. With an independent IDDQ measurement unit per device power supply, this will provide the Ocelot Test System the capability to concurrently perform high-speed IDDQ tests on up to thirty-two test sites.
Xilinx Inc. has joined IMEC's new industrial affiliation program (IIAP) that focuses on technology for reconfigurable systems. Xilinx is the first organization to join the IIAP. Through this program, IMEC will be applying its expertise in design technology for reconfigurable computing platforms to Xilinx FPGAs.
The mission of the reconfigurable systems IIAP is to build design technology that enables the programming of heterogeneous reconfigurable platforms with the same ease of use as current technology allows for general-purpose processors. Key activities include the development of an operating system that enables true hardware/software multitasking and the integration of interconnect networks on silicon for task-level reconfiguration in reconfigurable hardware.
Within this program, IMEC and Xilinx Research Labs will collaborate in developing a programming environment for reconfigurable systems based on the VIRTEX-II Pro devices as well as future devices. This programming infrastructure will provide support for seamless hardware/software multitasking in future reconfigurable computing platforms. The partial and dynamic reconfiguration capabilities of Xilinx FPGAs will be exploited in full to achieve that goal.
Monterey Design Systems has been issued patents numbered US 6,442,743, US 6,446,239, US 6,449,756 and US 6,449,761 by the United States Patent and Trademark Office bringing the company's patent total to eleven. The patents apply to the physical IC design technology that drives Monterey IC Wizard hierarchical design planning, Sonar physical synthesis and prototyping, and Dolphin physical implementation products.
Two of the new patents are key to Monterey's Progressive Multi-objective Refinement (PMR) technology. This approach to physical implementation provides for simultaneously optimizing the design for multiple criteria and progressive refining the chip implementation until all requirements are met. Monterey does not separate physical implementation into discrete, sequential steps performed by multiple, disparate point tools, as do all other vendors. Rather, all construction and analysis operations are performed simultaneously.
Two further patents were awarded for Monterey's hierarchical design planning technology. IC Wizard provides automated design planning capabilities that can improve die size and turnaround time on multi-million gate hierarchical SOC designs.
Ansoft Corporation has been ranked as one of 50 fastest growing technology companies in Southwestern Pennsylvania by Pittsburgh Technology Council awarded at the group's sixth-annual Tech 50 award ceremony at Carnegie Music Hall in Pittsburgh, Penn. The Pittsburgh Technology Council gives the Tech 50 award to high-tech companies in Southwestern Pennsylvania that demonstrate financial growth, advancement in product development or sales, corporate citizenship, job growth/retention, and innovation.
Magma Design Automation Inc. established sales and support offices in Korea to support its major customers in the Korean market. Magma's Korea office will be in Seoul and will be headed by Y.G. Jung, recently named regional sales director of Magma's Korea operations. Prior to joining Magma, Jung was the sales manager of Synopsys Korea where he was responsible for many major accounts. He previously held sales positions with Antrim, Texas Instruments, Mentor Graphics and LG in Korea.
In additional news from IMEC, the European microelectronics R&D center said it is setting up a 300mm silicon research platform initiative to perform advanced process research at least two generations ahead of manufacturing. The initiative will serve several development organizations worldwide. A first important step has been achieved with the decision of the local government to grant funding of 37.18 million for the construction of the clean room.
To address the huge challenges resulting from the changing research environment, IMEC plans to set up a centralized 300mm silicon research platform. The initiative is based on IMEC's expertise and track record and will serve several development organizations worldwide. The goal of the research platform is to demonstrate novel device architectures and to perform research on process steps and modules. The advanced process research will run 2 to 3 technology nodes ahead of manufacturing.
The research fab will be very flexible and will operate at ultra-short cycle time. It will be built around the world's most advanced lithography clusters such as 157nm and EUV. To share common facilities, infrastructure and metrology tools and to use available human resources, the new fab will be located adjacent to current IMEC facilities.
Within this research platform, IMEC will continue its current business model, based on a sharing of cost, risk, talent and IP. Strategic long-term partnerships with a core set of equipment suppliers and major IC manufacturers will be set up to carry the investments. A first important step has been achieved with the investment of 37.18 million by the local government.
This new lab will also free up space in the current 200mm clean room to perform research in a broad range of nano-technology domains. This nano-research is important in preparation of the post-silicon era and will have numerous different applications in new industries and spin-offs.
Numerical Technologies, Inc. reported that one of its directors, Roger Sturgeon, has been honored with an award by industry association, Semiconductor Equipment and Materials International (SEMI). Presented at the annual SEMI dinner in San Jose, Calif., the award acknowledges Sturgeon's outstanding contribution to the advancement of semiconductor manufacturing technology.
A Numerical director since January 2000, Sturgeon has spent his career engaged in the ongoing development of cutting-edge solutions to suitably handle and transform design information into manufacturable ICs. More than three decades ago, he led the original GDSII team -- a cadre of technologists that produced the definitive IC design information format that enabled the efficient representation of design data, allowing it to be viewed, manipulated and shared between tools. It is his work with this industry-standard technology that earned him last night's SEMI award.
In 1986, Sturgeon co-founded Transcription Enterprises Limited-a leading developer of mask data preparation (MDP) software -- which was acquired by Numerical just before the company went public in early 2000. Under his stewardship, the company's signature CATS software became a fixture in virtually every IC company throughout the world -- exerting a market dominance that continues today. Since joining Numerical's board, he has brought leadership and vision to the company's CATS division while becoming a key moderator in the industry-wide debate on the challenges of handling subwavelength design data.
The 40th Design Automation Conference (DAC) has issued a call for papers for regular technical papers, special topic sessions, panels, tutorials and university design contest entries. The annual conference, which promotes advances in design automation software and hardware for electronic systems, will be held June 2 to 6, 2003 at the Anaheim Convention Center in Anaheim, Calif. Authors are invited to submit original technical papers describing recent and novel research or engineering developments in all areas of design automation for the Design Methods or Design Tools Tracks, or for Embedded Systems Topics. The paper submissions deadline is Friday, December 6. The submission site is
scheduled to open Monday, October 21. Panel and special session proposals will be accepted through Monday, November 4, 2002. That submission site is scheduled to open Friday, October 4.
The Student Design Contest is an invitation to students to submit descriptions of original electronic designs, either circuit level or system level. Two categories of designs are eligible for awards -- operational and conceptual. For operational designs, proof-of-implementation is required. A complete simulation is necessary for conceptual designs. Designs must be part of the student's university studies and must have been completed after June 2001. Selected designs will be presented at the conference. Student Design Contest submissions must be submitted by Friday, December 20, 2002.
Notification of acceptance for all will be made by Friday, February 28, 2003. For more information, call (303) 530-4333, or visit the DAC website for more specifics on submission requirements. The site is located at: http://www.dac.com.
Electronic system-level (ESL) design solution and methodology provider Summit Design, Inc. will present a seminar on ESL Design on October 24 at the Westin Hotel in Santa Clara, California. The company said that the half-day seminar, beginning at 8:30 A.M., would demonstrate and discuss new tools and methodologies to design and manage complex semiconductor design, accelerate RTL flow through fast verification and leverage existing investment in C/C++ and SystemC technology.
The Annual EDA Consortium Phil Kaufman Award Dinner will be held Tuesday, November 12, 2002 at the San Jose Fairmont Hotel, 6:00 PM in the Club Regent Room.
Ansoft will be conducting seminars in Phoenix, LA, Irvine, San Jose, Portland, Ottawa, Boston, Philadelphia, Wash. DC, Dallas and Denver during the month of October. The seminar is entitled, “Empowering Profitability—a workshop for Signal Integrity, Radio Frequency, Microwave, and Optical designers.” Engineers attending will be taught techniques to simulate: 10 Gigabit, XFP Optical Modules, Low-Noise Amplifiers and Elliptic Filters, Power Integrity for High-Speed PCBs, Advance VCOs, Sub-Harmonic Mixers, LTCC Modules for Communication Systems, Full-Wave Package Analysis, Frequency-Selective Surfaces and High-Density RFIC Interconnect. For more information, visit,
The deadline for proposing papers for the Design & Verification Languages Conference and Exhibition (DVCon) is October 15, 2002. DVCon 2003 will be held February 24-26, 2003 at the DoubleTree Hotel in San Jose, California.
DVCon is the new name for the HDL/OVI conference, which will celebrate its 12th anniversary session in 2003. (It began as Open Verilog International and then merged with the VHDL International to become the International HDL Conference.) HDLCon's scope may have started with Verilog and VHDL, but the conference scope has evolved as new languages have emerged, to now include VERA, E & SystemC.
Proposals are invited for any of the following types of presentations:
Technical papers on using Hardware Description Languages (HDLs)
Technical papers on using Hardware Verification Languages (HVLs)
In-depth tutorials on design and verification techniques
Educational panels on trends in design and verification
Details on submitting a paper, tutorial or panel proposal, along with suggested topics, can be found on the Design & Verification Conference web page at
The 11th IP based SOC Design Workshop will take place in Grenoble, France on October 30 and 31, 2002. Among 100 submissions the best technical contributions have been selected to bring together a high level working conference unique on hot topics such as “Impact of Submicron Technology,” “IP Management and Collaborative Design,” “Verification IP,” “IP Business Models,” and “Platform Based Design and Embedded System.”
The program has outlined most of the foremost players actively involved in this field planning to deliver their latest products and major fact announcements at this event. Please refer to the Online Program:
Keynote speakers include: John Chilton, senior vice president and general manager of Synopsys IP and Systems business unit, Michael Kaskowitz, General Manager and VP of the IP Business unit of Mentor Graphics, Thierry Pfirsch, Core Competence Manager for IP at Alcatel and Jim Tully, Chief Analyst from Gartner Dataquest.
On October 31st the “Best IP/SOC” trophy sponsored by ST Microelectronics will be given involving a selection among eight candidate companies. In addition the “IP based SOC Design Workshop” has an exhibition attached include Accent, Artisan Components, Axis Systems, Cadence Design Foundry, CoWare, Denali Software, Design And Reuse, Dolphin Integration, Ericsson Technology Licensing, GeTeDes, Infineon Technologies, Jennic, OCP-IP, ProDesign, SuperH, Synchronicity, Synopsys, VCX and Verisity.
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-- Ann Steffora, EDACafe.com Contributing Editor.