January 09, 2012
Blurring the line between EDA & Test
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Russ Henke - Contributing Editor


by Russ Henke - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

  • 42 are issued, 17 pending in United States, China, Taiwan, Japan, and EPC.
  • 21 Issued in United States for 1T, 2T, and 3.5T anti-fuse bit cell technologies. 
  • 5 for 1T, 15 for 2T, and 1 for 3.5T

  •  



    Figure 2. Anti-Fuse Patent Portfolio


     

     

    Comparing NVM Alternatives

    The competitive advantage of anti-fuse is best illustrated by comparing it with other embedded NVM technologies available in the market:
  • Embedded Flash solutions where data is represented as a charge;
  • Floating gate or charge trapping solutions that likewise represent data as a charge;
  • Electrical fuse solutions that blow a metal link or the silicide on a poly line to represent data as a change in resistance;
  • Via or diffusion ROM that represent data as a short or open at a given node in a memory array fabricated in the metal layer of a chip during manufacture.

  • Embedded Flash, the most expensive and most flexible of the embedded NVM technologies, is ideal for code and data storage that changes often. It can require at least 10 additional mask steps. The higher upfront cost of the technology is offset by high endurance allowing frequent and a large number of read-write cycles. Commonly found in microcontrollers (MCU) it provides flexibility to end applications to produce multiple configurations from one product.


    For example, an MCU chip manufacturer may produce a low end 8-bit MCU for a dozen different appliance manufacturers.  By producing a base MCU and adding different features for each of the different customers in flash, the MCU supplier eliminates the need to manufacture a different MCU for each customer—thus saving silicon cost and eliminating the inventory problem of stockpiling different products for different customers.  Both the vendor and the customer benefit from the flexibility, respectively, to control inventory and provide differentiation.


    An alternative to flash is floating gate or charge trapping solutions in the form of the stacked-gate 1T cell, a CMOS transistor with one floating gate and one contacted gate overlapping each other. See Figure 3. Insulated by a high quality oxide from the contacted gate, the floating gate is programmed by channel injecting electrons and erased by allowing the trapped electrons to escape. The presence or absence of electrons in the floating gate is read as a “1” or “0”. Like flash the floating gate memory can be erased and electrically programmed.






    Figure 3. Floating Gate NVM Technology


     

    However, both flash and the floating gate solution requires additional masks and processing steps on top of the standard CMOS logic process though the latter requires fewer than former.  How much additional cost a design requiring an embedded re-programmable NVM can bear will determine if an application will opt for the flash or floating gate alternative.  Having to add processing steps to the standard logic CMOS process means that these two solutions will not be available at the latest process node. Typically flash on logic CMOS will lag standard logic CMOS three generations whereas floating gate may be one or two
    generations behind.


    Another alternative NVM storage technology is electrical fuse (eFuse) made of polysilicon or metals.  The metal eFuse is a one-time programmable memory programmed by applying a high current to rupture a conductive link or make its resistance significantly higher.  The reliability of an eFuse is a concern because debris and shards can cause the fuse to grow back over time.  See figure 4. The polysilicon eFuse with Cobalt or Nickel silicide on top is programmed by a well-known reliability mechanism called electro-migration in which electron momentum pushes the silicide atoms out of the conductor link to produce a high resistance or open circuit.






    Figure 4. Poly Fuse Technology


    The eFuse is typically custom-designed and provided by the foundry as a macro, thus affording the designer a lower cost solution. However, migrating a design containing an eFuse from one foundry to another becomes problematic. Most fuses are programmed during wafer fabrication with stringent power requirements for programming.  The eFuse bit cell is the largest of the standard CMOS NVM technologies. If an application calls for higher bit density, greater than 4Kb, another 4Kb eFuse increment begins to take up too much area of the SOC.


    Finally, among all the NVM alternatives, ROM is the lowest cost technology available, however, it is the least flexible of all. ROM is typically used for storing code that does not change such as audio recording of “Happy Birthday” in a musical greeting card or fonts in an ink jet printer. The ROM is programmed as part of wafer fabrication, thus, the content can only be changed by producing a new mask layer.


    The anti-fuse NVM addresses all the shortcomings of the four alternative NVM solutions.  Unlike flash or other charge trapping NVM solutions, anti-fuse requires no additional cost over standard CMOS and scales easily with each new generation of process technology. Unlike the eFuse and ROM solutions, anti-fuse can be programmed in the final package in the field with a simple write command.  And, unlike eFuse and ROM, anti-fuse is portable across multiple foundries and multiple processes from 180nm to 28nm.  Finally, of all the NVM solutions anti-fuse is the most tamper-resistant, even to invasive attacks and scanning electron microscope
    observation.


    Growing Demand for Embedded NVM


    Fueling the company’s success and growth is the increasing consumption of digital multimedia content on portable devices—smart-phones and tablets and consumer electronics devices in the home—Internet TVs and web-enabled set-top boxes. Further demand for the company’s NVM intellectual property (IP) is coming from being incorporated in microcontrollers (MCU) targeting automotive applications. Over a hundred MCU’s provide control of engine, transmission power, auto body, cabin environment, lamp, security, and audio entertainment in a typical new car today.  Finally, the number of analog and mixed signal circuits being incorporated on
    next generation system on chip (SoC) designs continues to grow producing additional consumption of Kilopass NVM IP


    According to a Global Industry Analysts, Inc. market research report published in May of 2011, the global smart phones market will reach over 1.6 Billion units by 2017.  This growth is being fueled by a plethora of functionality smart phones provide such as data services:  applications, multimedia, location-based services.  The market research firm sees near-field communications that enable wireless purchases, electronic wallet, etc. becoming prevalent in the next generation of devices. All this functionality is fertile ground for theft and fraud by hackers exploiting the technology.  NVM memory within these portable devices provides
    tamper-resistant storage for personal identification numbers (PINs), encryption keys, and other private information.  However most NVM technology is relatively easy to hack.


    Kilopass’ embedded non-volatile memory cannot be hacked using passive, semi-invasive, and invasive methods. Due to the nature of the technology, it is difficult to determine the content of the memory. Passive techniques including using current profiles to determine the word pattern are unsuccessful because the bit cell current for “0”s and “1”s are much smaller than the current required for sensing or to operate the peripheral circuits in order to read the memory. One cannot determine the pattern of the word being read.  Invasive techniques including backside attacks or scanning electron microscope passive voltage contrast are
    unsuccessful because it is very difficult to isolate the bit cell since it is connected in a cross point array. Furthermore, it is difficult using chemical etching or mechanical polishing to locate the oxide breakdown. In a cross-section or a top view, it is difficult to determine which bit is programmed.




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    -- Russ Henke, EDACafe.com Contributing Editor.




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