50 Ways to Cleave to Others
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50 Ways to Cleave to Others

It's refreshing to hear that someone in EDA Land, other than Cadence, has recently announced complex M&A news. The truth of the matter is, of course, that M&A news emerges regularly from numerous companies in EDA. For whatever reason however, closer press attention is often paid when this type of news comes from Cadence - and that coverage, as we all have seen of late, is not always complimentary.

It reminds me of the complaint I saw from Rod Stewart recently. He's unhappy that the press is critical of him for dating a much younger woman, where as the press criticizes Sir Paul McCartney not at all for dating and marrying a much younger woman. Stewart wants to know where the justice is in all of that. Well, where is it written that the press is always scrupulously just?

In any case, criticism from the press - harsh or otherwise - is not the subject of today's copy. The subject is a recent multi-faceted M&A announcement from Magma, excerpted below:

Magma Design Automation Inc. announced October 20th the acquisitions of Silicon Metrics and Random Logic Corp. by merger, and an agreement to license patents and add key technologists from Circuit Semantics Inc.

Silicon Metrics develops characterization and modeling tools for standard cells, memories, and complex I/Os. Silicon Metrics' technology will form the foundation of Magma's Silicon Correlation Division.

Random Logic's QuickCap extraction tool is a widely used and highly accurate extraction tool, which is a 3D field solver and extraction product. QuickInd, an inductance extraction tool, was launched by Random Logic last year and QuickCap provides an API, which is licensed and distributed by multiple EDA suppliers.

Magma also announced it has licensed patents from Circuit Semantics (CSI) for technology the company developed for in-place cell characterization and chip-level timing analysis for structured-custom methodologies. Magma also hired key technology personnel from Circuit Semantics for Magma's development team.


Given the extent of this news, all encapsulated into a single announcement, I was glad to have a chance to discuss these multiple developments with Nitin Deo, Vice President of Product Marketing at Magma, during an October 30th phone call some 10 days after the news was announced.

Q: The Press Release seems to be a bit ambiguous as to whether Silicon Metrics and Random Logic have been acquired or have merged with Magma?

A: Both Silicon Metrics and Random Logic were acquired. We now essentially own their assets, their patents, their proprietary IP, [and employ] their personnel.

[With regards to CSI], we essentially acquired rights to all of their patents. We were mainly interested in the technology aspects of CSI and obtaining the rights to develop along those lines. The patents are owned by the CSI entity, but we are assuming the use of those patents. I don't believe we have exclusive rights, but we do have the right to use them within our technology. It's called having access to the patents.

Q: Why not acquire CSI outright?

A: There were some issues related to pending legalities with other operations within CSI, that [guided us in this direction]. What we were interested in was the patents and nothing else.

Q: Why announce the acquisitions and the licensing within the same Press Release?

A: To a certain extent, it just so happened that they all came together at the same time from a technology development perspective. We believe we will now provide solutions to our customers that will take them further along in their quest for higher quality products, with better timing and closer correlation with the silicon.

Q: Does Magma have set procedures in place for assimilating technology and personnel?

A: Yes we do. We have done this in the past - acquired a couple of companies. [In the case of] Random Logic, we will assimilate their personnel into our R&D, our marketing, and so on. As far as the technology is concerned, we'll make sure that we integrate it [into our existing initiatives] wherever we see the most [benefit].

With Silicon Metrics, their technology is complementary to ours. Their technology, for example, does more accurate characterizations of standard cells and structures, which then gives better timing models to our system. It's not necessary to integrate that technology within our design system, so we've kept Silicon Metrics as the Silicon Correlation Division, a [stand-alone business unit] headquartered in Texas.

As a company, we're in a global environment anyway. We've got global centers all over the world now, where they all report into the central R&D here in [Silicon Valley]. The Silicon Correlation Division will maintain their own R&D and marketing facilities within that division.

Q: What is the official headcount at Magma now?

A: We're not disclosing that information at this time.

Q: When will the events be finalized, the final papers filed?

A: It will all be finalized within a few weeks. The Board of Directors has signed off on the deals.

Q: Are there more similar announcements coming up in the near future?

A: We're not commenting at that.

Q: Who is going to buy the champagne when it's all completed?

A: (A long, long chuckle) No comment.

(Pause) Although, actually, one of the things we're hoping is that the customers will buy the champagne. We have really come up with a technology roadmap that will show them how we can further and maximize their performance overall and quality of results.

Just the other day, I was visiting a customer, who used our tools to achieve 440 MHz, where they had only been able to achieve 400 MHz before [using other tools]. With these new technologies, we'll hopefully help them take [their performance] to 500 MHz. We think the customers should be buying the champagne - and drinking the champagne.

(Editor's Note - Check your 30 Days to a Better Vocabulary. Interestingly enough, the word 'cleave' has two, diametrically opposed meanings.)



Industry News -- Tools and IP

Advanced SoC Platform Corp. (ASPLA) and Silicon Canvas, Inc. (SCI) announced that ASPLA has adopted Laker T1 as its 90-nanometer test chips development platform. ASPLA is a collaborative research organization comprising Fujitsu, Matsushita, NEC Electronics, Renesas, Toshiba, and five other companies. The ten member companies say they are working together to establish a design and manufacturing technology platform to drive the fabrication of semiconductor devices in 90-nanometer and lower process technologies in Japan. Hau-Yung Chen, President at Silicon Canvas, is quoted in the Press Release: “ASPLA is indeed one of its kind in pioneering technology advancement as well as business innovation for the next era. We are very glad to partner with ASPLA. Through Laker T1, we offer automation and correct by construction test chip layout implementation resulting in a standardized test chip platform that can be re-used at any process derivatives and future technology nodes.”

Apache Design Solutions announced several customer success stories in Q3 2003. Apache says its early customers achieved “first-pass silicon success, with measured data correlated to RedHawk's results.” The designs included a 90-nanometer DSP chip, a 130-nanometer networking design, and a 150-nanometer Ethernet chip. Also mentioned in the Press Release - an 18-million gate design from a fabless company and a design, which "involved the SPICE-accurate analysis of over 300 I/O's switching simultaneously."

For the engineers among you, the Press Release also says: “For many years, static power analysis has been used only during the verification stage of most designs, as final signoff before fabrication. The leading semiconductor companies doing advanced 130-nanometer and 90-nanometer designs have realized that the cost of over-design (die size and routability) to avoid power issues in the verification stage can no longer be tolerated, particularly as margins are reduced when power supplies drop to one volt or less. Also, dynamic effects associated with simultaneous switching, decoupling capacitance, package RLC parasitics, and even on-chip inductance need to be considered. Apache's DvD technology enables identification and repair of these dynamic hot spots early in the design phase and through final verification … without over-design.”

Hier Design Inc. announced that the company's PlanAhead hierarchical floorplanning and analysis software now supports the Xilinx Virtex-II Pro, as well as the Xilinx Virtex-II and Spartan-3 device families. Jerry Banks, Director of Global Alliances at Xilinx, is quoted in the Press Release: “With the exclusive support to Xilinx Virtex-II Pro, Virtex-II, and Spartan-3 devices, the PlanAhead software provides tight control to Xilinx device utilization.”

Ixia announced it has been selected by Accelerated Technology (AT), Embedded Systems Division of Mentor Graphics, to accelerate the IPv6 protocol development in the AT Nucleus NET networking product. Per the Press Release: “Ixia's ANVL (Automated Network Validation Library) is a data network testing product that validates the protocol implementations and operational robustness of networking devices.” The ANVL IPv6 Conformance Test Suites provides coverage for IPv6 protocols by way of various conformance tests for routing, bridging, Transport (TCP), IP storage, traffic engineering (MPLS), network security, tunneling, multicast, RMON, and IPv6.

LogicVision, Inc. announced ET Planner, developed in conjunction with Atrenta Inc., which the companies say is an automation tool that helps guide designers through the embedded test integration process. The product is intended for use at the RTL design stage, and “provides upfront guidance and compatibility verification between the design architecture and LogicVision's embedded test technologies. To reduce the chance of design iteration, LogicVision and Atrenta have jointly developed a new capability that is intended to eliminate any unpredictability of the embedded test integration process by providing upfront architectural verification at the RTL level. This new capability along with existing RTL-level LogicVision DFT rule checking is packaged into one new tool, ET Planner, included in LogicVision's latest product LV2004.”

Mentor Graphics Corp. announced its Scalable Verification platform that the company says will merge standards support, new tools, and a design-for-verification methodology to minimize functional verification cycles and avoid costly re-designs. The new platform includes product enhancements that allow for verification at early stages in a design and is “centered” on the Mentor ModelSim simulator. The Press Release described the Scalable Verification platform as “the most comprehensive EDA vendor tool platform for functional verification today.”

The platform includes standards support for Verilog 2001, VHDL, SystemVerilog (first phase of v3.1), SystemC 2.0.1 (including SystemC Verification Library 1.0) and the Property Specification Language 1.0 (PSL). The platform also includes a new version of the VStation emulation series, VStationPRO, and VStationTBX. Additionally, a new product from The MathWorks called Link for ModelSim, provides a direct link between Simulink and MATLAB.

Neolinear, Inc. announced that ATI Technologies, Inc. has chosen NeoCircuit for advanced analog and RF circuit sizing. Neolinear says that their tool, used in a complete design flow, “automatically sizes advanced analog, custom mixed-signal, or RF circuit topologies to a set of specifications using the customer's foundry of choice and simulation environment.” Raymond Li, Vice President of Hardware Engineering at ATI, is quoted in the Press Release: “Our evaluation of NeoCircuit demonstrates that this innovative tool provides design reuse and re-targeting capabilities that did not exist in our analog and RF design flow. We look forward to working with Neolinear to deploy NeoCircuit throughout our organization.”

Sequence Design announced it has received a patent for interconnect-driven design optimization. The patent is entitled Method and Apparatus for Interconnect-Driven Optimization of Integrated Circuit Design and, per the Press Release, is “a phased optimization methodology to speed design closure. The design is first 'pre-conditioned' to insure that no part of the circuit is operating outside of its specified range. This targets specific problem areas, or 'hot spots,' within the design that can be ranked using a unique algorithm to identify locations where performance improvements will have the greatest potential impact. Following this step, optimization of hold and set-up time violations is performed automatically. Fixes are performed with surgical precision to minimize the impact on the layout so additional iterations can be avoided. The new design methodologies described in the patent, include the work of co-authors, Douglas Kaufman, Dr. Vinay Srinivas, and Dr. Robert Mathews.”

The only remaining question - what exactly is “surgical” precision, because I'll bet surgeons like to brag about their “deep-submicron” precision. Anybody want to take that bet?

Semiconductor Manufacturing International Corp. (SMIC), the China-based foundry, and Virage Logic Corp. announced that SMIC has selected Virage Logic as its IP provider The new agreement will make Virage Logic's semiconductor IP Platforms available on SMIC's 0.13-micron CMOS process - this in addition to an earlier agreement on 0.18-micron technology. Sam Wang, President of SMIC Americas, is quoted in the Press Release: “With Virage Logic's ability to respond 24/7 and proven track record of superior customer support, we can better service our customers to help them meet their time-to-market and time-to-volume pressures without sacrificing quality."

True Circuits, Inc. (TCI) announced that NEC Electronics Corp. has implemented a TCI clock generator PLL in a new SPI-4.2 interface hard macro fabricated in NEC's 130-nanometer process technology. Hideya Horikawa, Senior Design Engineering Manager at NEC Electronics America, is quoted in the Press Release: “The performance of the TCI PLL will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems.”

Virtio Corp. announced developers using the (take a deep breath) Metrowerks CodeWarrior Development Studio ARM ISA Edition for Hardware Board Bring-Up, Version 2.0 will now have the option to select from one of several Virtio Softboards, including the VPXS for the Intel XScale microarchitecture, the VPOM-1510 for the Texas Instruments OMAP1510 platform, and theVPAG for generic ARM 7 and 9 cores. The companies say this is the second Metrowerks product to include Virtio Softboard technology as a result of the company's earlier licensing agreement with Virtio.

Again for your inner engineer: “The Softboards are complete software implementations of the reference platforms that are capable of running real target binaries. With these Softboards, embedded application developers may chose the architecture they are targeting to test and debug their native ARM applications on an accurate representation of the actual hardware without having to purchase costly, in-demand reference boards.”



Coming soon to a theater near you

ICCAD 2003 - The conference is coming up soon, during the week of November 10th at the DoubleTree Hotel in San Jose. This is an IEEE-sponsored event that offers authentic opportunities to listen and learn from some of the best in the industry, those with expertise in both theory and application. Now in its 21st year, organizers say the keynote address will be given by Stanford University's Mark Horowitz, and will discuss “CMOS, Scaling, and the Future.” All told, the 5-day conference will feature 129 papers (out of more than 490 submissions) scattered across 37 technical sessions and 6 tutorials. Per the organizers, the International Conference on Computer Aided Design always strives to be as “international” and “multi-disciplinary” as the worlds of design and CAD are themselves. That means that no matter who you are, or where you are, you should be coming. ( www.iccad.com)



Newsmakers

Accellera announced that its corporate members have elected a slate of congenial and experienced officers - Dennis Brophy, Director of Strategic Business Development at Model Technology (Mentor Graphics) was elected Accellera's Chair for a fourth term. Shrenik Mehta, Director of Frontend Technologies - ASICs & Processors at Sun, was re-elected Vice Chair. Dave Kelf, Vice President of Marketing at Novas Software, was elected Treasurer. And Karen Bartleson, Director of Interoperability at Synopsys, was re-elected Secretary for a fourth term.

The organization also announced its plans for the next year, which happily include sending the Accellera SystemVerilog design language standard to the IEEE for standardization. Per the Press Release: “In the coming year, Accellera plans to enhance the process it uses to build and maintain electronic design standards with the IEEE and assign the copyright of SystemVerilog 3.1a to the IEEE for standardization consideration by the IEEE 1364 Working Group before the 41st [DAC]. Accellera's technical committees have plans in place to complete the unification of Accellera's Property Specification Language (PSL) with SystemVerilog 3.1 assertions to produce PSL 1.1, and synchronize the Accellera Verilog Analog/Mixed Signal (Verilog-AMS) design language standard with its SystemVerilog syntax.”

InTime Software Inc. announced it has appointed Jeff Goldman and Michael Whalen as Senior Sales Directors. Goldman has 20+ years' experience in IP and EDA sales. Previously he held positions at LogicVision, Wind River Systems, Vantage Analysis Systems, and Teradyne. Whalen has 14+ years' experience and previously held positions at Innologic Systems (now part of Synopsys), Segue Software, Ikos Systems (now part of Mentor Graphics), Quickturn Systems (now part of Cadence), and Xerox Corp. He also was a lecturer in the EECS Department at Loyola Marymount in Los Angeles, CA. Both Goldman and Whalen will report to InTime President and CEO Robert Smith.

MatrixOne, Inc. announced that they have established an OEM agreement with Cadence Design Systems. Under the exclusive agreement, Cadence will embed MatrixOne technology into their Product Lifecycle Management (PLM) solutions that will be marketed and supported directly by Cadence. The offerings are intended to help engineering teams collaborate on the development of PCB designs. The agreement is effective immediately and is described by the companies as a “significant milestone in the strategic joint initiative that MatrixOne and Cadence announced earlier this year.”

The Press Release also quotes Mark O'Connell, President and CEO at MatrixOne: “The structure of global electronics design and value chains are becoming increasingly complex and fragmented. Our relationship with Cadence provides collaborative product design solutions that customers can integrate seamlessly into their existing design environment. This enables them to balance their product development investments between their internal resources and their outsourced and off-shore design and manufacturing partners.”

Open Core Protocol International Partnership announced Cadence has joined the organization as a Sponsor Member and is a participant in OCP-IP's Working Groups, as well. Franck Seigneret, Texas Instruments' OCP-IP Governing Steering Committee member, is quoted in the Press Release: “The addition of Cadence to the Working Groups enhances an already highly-talented team drawn from members such as Nokia, Texas Instruments, and STMicroelectronics. The Verification Working Group looks forward to collaborating with [Cadence].”



In the category of ...

Girding for the wireless grid

IMEC (Inter-university MicroElectronics Center) calls itself “Europe's largest independent research center in the field of microelectronics, nanotechnology, enabling design methods and technologies for ICT systems.”

That's all well and good, but the more important thing is that this consortium of government, academia, and industry is located in the lovely university town of Leuven, Belgium - 40 minutes east of Brussels. There are more than 1200 technologists working away there, generating ideas and revenues via contracts with the Flemish government and various high-tech companies throughout the EU.

In some ways, IMEC is best thought of as a think tank; a lot of thinking goes on there. In September, they released an announcement - a mission statement if you will - that attempted to establish a roadmap indicating how IMEC hopes to “lay the foundations for ubiquitous wireless broadband communications” through research into the wireless grid. (see below)

Several weeks ago, I spoke by phone with Liesbet Van de Perre, Director of Wireless Technology at IMEC. She briefly explained the IMEC vision: “The basic idea here is that the user always wants more wireless functionality [from devices], but at the same time wants less power consumption. [Clearly] these are contradictions.”

“[To address the power issues], for instance my wired laptop could provide power to my wireless PDA. Lots of technology breakthroughs are needed to accomplish this. However, we believe it's the way to break through the physical limits of what you need. If you add the wireless concept to the wired concept, the amount of freedom you get and the savings you get in wireless communication power [will be marked].”

“[Meanwhile], we hope to take [conceptual] breakthroughs such as base station and client, or server and client, and evolve those to the wireless grid. Think of grid computing - you need the same concept for wireless communication. Each terminal or device would be a node on a wireless grid of devices. You would have [wireless access] no matter what device you use within your environment.”

“[In all of this], we're playing a role in the move to C-based design. There are [multiple] reasons for going with C or C++ [as a design language]. You can have your design optimized on as high a level as possible.”

“We're working on long term problems. We're setting up PhDs to solve these problems, [to attack] the fundamental research. One crucial component [we're examining today] is the low-power radio. In the end, we'll see the reconfigurability of these devices - reconfigurability is difficult, but RF MEMS can be made reconfigurable. [We're also looking at] flexible communication engine simulators - can we actually build a system with only a few components.”

“We think that the fundamental block you need is the same in all of these schemes. It's about [solving the] computation and communication [problems simultaneously].”

If you would like to read a much more detailed discussion on the topic, please go to the IMEC news page and read the Press Release dated September 30th. It will be worth your while.