February 25, 2008
First 4 weeks of Shock & Awe … then DVCon
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

This past week was the week Mike Santarini got laid off, John Cooley remembered his manners, Brett Cline forgot his, Wally Rhines proved (once again) he’s an engineer’s engineer, Tom Williams became an electron, Karen Bartleson became an advocate for peace, and Gary Smith admitted he doesn’t balance his checkbook.

More profoundly, however, this past week was the week that Cadence pulled out of DAC (see excerpt from the press release below). Though the news was not completely unanticipated, it still came as a shock – even after 4 weeks of shock and awe. Others may not agree, but I believe this decision will have far-reaching ramifications for the company, the conference, and the industry.

Meanwhile, and not coincidentally, this past week was also the week I finally learned the truth about design automation. The truth is that the big IDMs would (probably) get along just fine without the EDA industry, and that’s because they do so much friggin’ tool development in-house.

The truth is that the chip designers in the big IDMs not only have easy access to their own internal CAD-specific IT support, they also have easy access to the internal CAD tool developers themselves. Hence, the internal tool developers at the big IDMs learn from their in-house chip designers, and the chip designers learn from their in-house tool developers and the living is easy. The truth is that the big IDMs are often (always?) way ahead of the third party CAD tool providers in technology, methodology, and implementation because it behooves the IDMs to have it that way. Their existence and survival depends on it. The truth is that the IDMs don’t even think to turn to third-party CAD tool providers until their own CAD tools have reached such a level of sophistication that the IDMs can be comfortable letting third-party vendors provide the “commodity” sub-set of their total requirements. That the third-party tool vendors then undercut each other (to death?) on increasingly anorexic margins for those commoditized tools is of little concern to the IDMs. In fact, it’s to their benefit that the third-party vendors tear each other apart in attempts to get the attention and business of the IDMs. The truth is, if the price and service and accommodations aren’t just right, the IDMs can just go internal again and continue on with their own
in-house tool development and support. They’ve got the money, the knowledge, and manpower to do it.

And that’s the truth about design automation and the context for everything that follows here.

Hint: Click on “Print this article” up there on the right if you want to read this article all on one page.]


First there was Shock & Awe …

Four weeks ago: Cadence released sharply disappointing Q4’07 revenue numbers and predicted Q1’08 revenues would be closer to $280 million than the hoped-for $390 million. Cadence stock promptly plummeted 33%, the company’s market cap fell to its lowest level in 10 years, $2.9 billion (in contrast to its $6.4 billion market valuation at the height of last June’s unconfirmed Blackstone/KKR buyout rumors), and the financial press went gaga with headlines like, “Cadence: What Just Happened in the EDA Business?” The entire industry was implicated; SNPS, MENT, and LAVA tanked, as well.

Three weeks ago: IEEE’s annual solid state circuit extravaganza,
ISSCC, showcased a dazzling array of Latest & Greatest for the 3500 techno-wonks gathered in San Francisco, including:

The world’s first 2-billion transistor chip from
Intel, a 65-nanometer 16-core 32-thread processor from
Sun, novel techniques for on-chip gain and filtering functions from
Sony, power-down architectures for increased on-chip power efficiencies from
IMEC, an implantable amplifier for extraction of micro-Volt “brain biomarkers” from
Medtronic, an ultra-low power 45-nanometer multimedia processor from
TI, a 56-nanometer 2-bit-per-cell NAND Flash device with 34Mbits/s program throughput from
SanDisk &
Toshiba, a 45-nanometer 4Gbit 3D double-stacked multi-level NAND flash device from
Samsung, a 1-Volt wearable SOC for a wireless body-area-network monitor from
Toumaz Technology, and a full GSM SIP complete with RF, baseband, and power management from

* Three weeks ago, as well: EDAC hosted its annual CEO Forecast Panel in Silicon Valley. Despite plucky, niche-specific, bravado-laden claims from some – Jasper’s
Kathryn Kranen: “Design-based verification will take off!” Denali’s
Sanjay Srivastava: “2007 was the Year of the SoC!” MIPS’
John Bourgoin: “Long-term trends play into the IP market!” Synopsys’
Aart de Geus: “No doubt, we’ll do very well!” – only Mentor Graphics’
Wally Rhines had the courage (and recursion charts) to posit an actual growth number for the industry for 2008, an astonishingly anemic 2%.

Of course, Cadence’s long-suffering
Mike Fister, beaten into submission by The Street the previous week, had to admit: “Our customers are in recession and we’re worried.” But, he also noted that many continue to undervalue the worth of the tools his industry provides: “We’ve created value, [but some customers see] an opportunity to destroy that value, which is criminal.”

Sitting next to Fister, Kranen sharply retorted: The all-you-can-eat deals that characterize the business practices of the large EDA vendors exacerbate pricing pressures for the smaller vendors. Fister responded, “It’s a cop-out to say all-you-can-eat deals are prevalent.” And later, in apparent defiance of The Street as well, he added, “It doesn’t matter what the market says!”

Lest the report of the EDAC event be incomplete, the evening’s speakers also offered concrete suggestions. From
Kathryn Kranen: Customers are seeking the little ROI from less expensive tools, but they should be looking for the Big ROI from the massive improvements that come with tools that are worth breaking their flows for. From
John Bourgoin: The high growth rate [ahead] is in analog. From
Sanjay Srivastava (after running over prophecies of ESL with a freight train): We need to be bolder with the adjacencies. From
Aart de Geus (just returned from the annual pilgrimage to the World Economic Forum at Davos): We must learn to sell better, [because] we are an industry that adds value. From
Mike Fister: Automation is the key, [as well as] educating the customer. And from
Wally Rhines: Throughout the history of EDA, we’ve grown by solving new problems. There will always be profits from advancing the technology!

Three weeks ago, also: IEC’s
DesignCon took over the Santa Clara Convention Center. With more than 130 exhibitors on the floor, the exhibition hall was large, lively, and well attended. There was definitely energy there. [But, don’t take my word for it. Enjoy
Graham Bell’s video interviews with many of the vendors on the show floor at DesignCon.] Eight companies at the conference were honored with IEC DesignVision Awards, including Cadence (design tools), Mentor & Cadence together (for OVM), Amphenol TCS (interconnect), Altera (ICs), Rambus (IP), Lattice (FPGAs), Future Plus Systems (system-level design tools), and Agilent (test and measurement). Various panels at the conference were rich
in content and candor, including a discussion of the current ecosystem for semiconductor startups which was shockingly blunt in its evaluation of the shortage of both venture capital and profits in the industry today.

But the flip side of the emotional schizophrenia within the semiconductor industry was also on display at DesignCon, where a panel moderated by Forbes’
Elizabeth Corcoran discussed (read “showcased!”) exuberant employment and market opportunities in India.

Ganesh Guruswamy said they’ve got thousands of employees working at geometries ranging from 250-to-45 nanometers in the company’s centers of excellence for SOC and IP design in India. Cadence’s
Jaswinder Ahuja said Cadence has been underway for 20 years in India and an operation that Joe Costello once termed a “hidden jewel” is now a huge contributor to the company’s R&D. Wipro’s
Vasudevan Aghoramoorthy cited current statistics for his company: “We’ve grown significantly [over the last several years] and now have 18,000 engineers working for us in India.” And he reiterated the power of the consumer in India: “India as a market has exploded since the late 90’s. Ten years ago, no one would have believed that there could be 10 million new cell phone subscribers per month in India, but that’s today’s reality. And that doesn’t include replacement handsets!” Ahuja added: “It’s an acknowledged fact that
the BRIC economies [Brazil Russia India China] are now driving the global markets!”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.

Review Article
  • DVCon Troublemaker's Panel February 26, 2008
    Reviewed by 'Cedric Iwashina'
    Hi Peggy,
    At the DVCon Troublemaker's Panel, I thought that some of Gary Smith's observations/predictions were the most interesting.
    A few weeks ago at the EDAC CEO panel, you asked Mike Fister about the rumor last summer that Kohlberg Kravis Roberts and the Blackstone Group might possibly take Cadence private.
    On this year's Troublemaker's panel, Gary said that a large part of Cadence's recent financial shortfall was due to private equity (PE). Specifically, some of Cadence's largest customers were taken private over the last two years, e.g., NXP and Freescale. Now, the PE firms realize that they made a mistake and are losing money hand over fist. So, they've cut costs to the bone. As a result, they're not spending as much on EDA software as expected. Gary also said that, due to these financial debacles, PE firms were no longer interested in anything even remotely related to semiconductors, including EDA.
    Gary also said in physical implementation, Cadence needed to buy Magma, but probably couldn't afford it any longer after their precipitous drop in market cap. He said that Mentor/Sierra would be able to sustain a viable physical implementation business. And that AtopTech would most likely be acquired, probably by Synopsys.
    One last thing he said, that I found to be a bit strange, is that ESL continues to grow, but hasn't reached the "knee of the curve" in terms of market acceptance, yet. I think he said that it would reach that "knee" around 2012. That can't be good news for ESL companies.

      8 of 9 found this review helpful.
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  • What the *&!^? February 25, 2008
    Reviewed by 'Bob Smith'
    Peggy -
    This is a great article and dissection of the state of the EDA industry. No doubt the industry is going through very tough times and your article provides several different perspectives about why this is happening. Your obesrvation about the role the IDMs play in the food chain is very good, for example. While EDA may be on the "outs" now, it is clear that if semiconductor technology is going to continue to evolve, it will require new technical innovations to solve the tough problems in design, verification, and implementation. Some of this will come from within the large IDMs / semicos, but based on history we also know that a good part of the fundamental innovation will come from startups and academia. The question is ... can the fundamental business models that drive the industry change and evolve as well?

      7 of 10 found this review helpful.
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