November 03, 2003
50 Ways to Cleave to Others
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

It's refreshing to hear that someone in EDA Land, other than Cadence, has recently announced complex M&A news. The truth of the matter is, of course, that M&A news emerges regularly from numerous companies in EDA. For whatever reason however, closer press attention is often paid when this type of news comes from Cadence - and that coverage, as we all have seen of late, is not always complimentary.

It reminds me of the complaint I saw from Rod Stewart recently. He's unhappy that the press is critical of him for dating a much younger woman, where as the press criticizes Sir Paul McCartney not at all for dating and marrying a much younger woman. Stewart wants to know where the justice is in all of that. Well, where is it written that the press is always scrupulously just?

In any case, criticism from the press - harsh or otherwise - is not the subject of today's copy. The subject is a recent multi-faceted M&A announcement from Magma, excerpted below:

Magma Design Automation Inc. announced October 20th the acquisitions of Silicon Metrics and Random Logic Corp. by merger, and an agreement to license patents and add key technologists from Circuit Semantics Inc.

Silicon Metrics develops characterization and modeling tools for standard cells, memories, and complex I/Os. Silicon Metrics' technology will form the foundation of Magma's Silicon Correlation Division.

Random Logic's QuickCap extraction tool is a widely used and highly accurate extraction tool, which is a 3D field solver and extraction product. QuickInd, an inductance extraction tool, was launched by Random Logic last year and QuickCap provides an API, which is licensed and distributed by multiple EDA suppliers.

Magma also announced it has licensed patents from Circuit Semantics (CSI) for technology the company developed for in-place cell characterization and chip-level timing analysis for structured-custom methodologies. Magma also hired key technology personnel from Circuit Semantics for Magma's development team.

Given the extent of this news, all encapsulated into a single announcement, I was glad to have a chance to discuss these multiple developments with Nitin Deo, Vice President of Product Marketing at Magma, during an October 30th phone call some 10 days after the news was announced.

Q: The Press Release seems to be a bit ambiguous as to whether Silicon Metrics and Random Logic have been acquired or have merged with Magma?

A: Both Silicon Metrics and Random Logic were acquired. We now essentially own their assets, their patents, their proprietary IP, [and employ] their personnel.

[With regards to CSI], we essentially acquired rights to all of their patents. We were mainly interested in the technology aspects of CSI and obtaining the rights to develop along those lines. The patents are owned by the CSI entity, but we are assuming the use of those patents. I don't believe we have exclusive rights, but we do have the right to use them within our technology. It's called having access to the patents.

Q: Why not acquire CSI outright?

A: There were some issues related to pending legalities with other operations within CSI, that [guided us in this direction]. What we were interested in was the patents and nothing else.

Q: Why announce the acquisitions and the licensing within the same Press Release?

A: To a certain extent, it just so happened that they all came together at the same time from a technology development perspective. We believe we will now provide solutions to our customers that will take them further along in their quest for higher quality products, with better timing and closer correlation with the silicon.

Q: Does Magma have set procedures in place for assimilating technology and personnel?

A: Yes we do. We have done this in the past - acquired a couple of companies. [In the case of] Random Logic, we will assimilate their personnel into our R&D, our marketing, and so on. As far as the technology is concerned, we'll make sure that we integrate it [into our existing initiatives] wherever we see the most [benefit].

With Silicon Metrics, their technology is complementary to ours. Their technology, for example, does more accurate characterizations of standard cells and structures, which then gives better timing models to our system. It's not necessary to integrate that technology within our design system, so we've kept Silicon Metrics as the Silicon Correlation Division, a [stand-alone business unit] headquartered in Texas.

As a company, we're in a global environment anyway. We've got global centers all over the world now, where they all report into the central R&D here in [Silicon Valley]. The Silicon Correlation Division will maintain their own R&D and marketing facilities within that division.

Q: What is the official headcount at Magma now?

A: We're not disclosing that information at this time.

Q: When will the events be finalized, the final papers filed?

A: It will all be finalized within a few weeks. The Board of Directors has signed off on the deals.

Q: Are there more similar announcements coming up in the near future?

A: We're not commenting at that.

Q: Who is going to buy the champagne when it's all completed?

A: (A long, long chuckle) No comment.

(Pause) Although, actually, one of the things we're hoping is that the customers will buy the champagne. We have really come up with a technology roadmap that will show them how we can further and maximize their performance overall and quality of results.

Just the other day, I was visiting a customer, who used our tools to achieve 440 MHz, where they had only been able to achieve 400 MHz before [using other tools]. With these new technologies, we'll hopefully help them take [their performance] to 500 MHz. We think the customers should be buying the champagne - and drinking the champagne.

(Editor's Note - Check your 30 Days to a Better Vocabulary. Interestingly enough, the word 'cleave' has two, diametrically opposed meanings.)

Industry News -- Tools and IP

Advanced SoC Platform Corp. (ASPLA) and Silicon Canvas, Inc. (SCI) announced that ASPLA has adopted Laker T1 as its 90-nanometer test chips development platform. ASPLA is a collaborative research organization comprising Fujitsu, Matsushita, NEC Electronics, Renesas, Toshiba, and five other companies. The ten member companies say they are working together to establish a design and manufacturing technology platform to drive the fabrication of semiconductor devices in 90-nanometer and lower process technologies in Japan. Hau-Yung Chen, President at Silicon Canvas, is quoted in the Press Release: “ASPLA is indeed one of its kind in pioneering technology advancement as
well as
business innovation for the next era. We are very glad to partner with ASPLA. Through Laker T1, we offer automation and correct by construction test chip layout implementation resulting in a standardized test chip platform that can be re-used at any process derivatives and future technology nodes.”

Apache Design Solutions announced several customer success stories in Q3 2003. Apache says its early customers achieved “first-pass silicon success, with measured data correlated to RedHawk's results.” The designs included a 90-nanometer DSP chip, a 130-nanometer networking design, and a 150-nanometer Ethernet chip. Also mentioned in the Press Release - an 18-million gate design from a fabless company and a design, which "involved the SPICE-accurate analysis of over 300 I/O's switching simultaneously."

For the engineers among you, the Press Release also says: “For many years, static power analysis has been used only during the verification stage of most designs, as final signoff before fabrication. The leading semiconductor companies doing advanced 130-nanometer and 90-nanometer designs have realized that the cost of over-design (die size and routability) to avoid power issues in the verification stage can no longer be tolerated, particularly as margins are reduced when power supplies drop to one volt or less. Also, dynamic effects associated with simultaneous switching, decoupling capacitance, package RLC parasitics, and even on-chip inductance need to be
considered. Apache's DvD technology
enables identification and repair of these dynamic hot spots early in the design phase and through final verification … without over-design.”

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-- Peggy Aycinena, Contributing Editor.

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