Explicit and implicit X sources (X assignments in RTL and non-resettable flops, respectively) in the designs can lead to many challenging issues for design verification, such as masking real design errors and causing RTL-to-netlist simulation mismatches. Depending on coding styles, simulation results can be X-pessimistic which lead to unnecessary unknown values; or X-optimistic which results in known values when they should have been unknown. Design and verification teams write properties to trap Xs or instrument 2-value simulation with random initialization to avoid X ambiguity in order to detect design errors. However, these approaches take considerable amount of manual and computational resources without offering the complete confidence of X robustness.
Ascent PBV offers a multi-faceted solution that addresses the problem through structural and formal analysis, as well as by augmenting simulation using Ascent SimPortal. Explicit and implicit X sources are automatically detected. Innovative formal techniques are used to prove X-optimism safe designs. Ascent SimPortal can augment simulation to detect X-excitation, control X-pessimism, as well as eliminate X-optimism without loss of efficiency. It is the first automatic and comprehensive solution to detect and debug design errors and RTL/netlist simulation mismatches.
"Real Intent, as the leader in providing automatic functional verification solution for ASIC and FPGA designs, has been approached by many customers with issues related to X-handling in their designs," commented Prakash Narain, President and CEO at Real Intent. "Ascent PBV meets the needs and rises to the challenges by using multiple innovative technologies to ensure X-robust designs. We deliver verification confidence to our customers by turning their verification unknowns into the known."
Pricing and Availability
Ascent PBV is available worldwide in August. For complete product and pricing information, please email Email Contact.
Visit Real Intent at Booth 1728, at the 2009 Design Automation Conference (DAC), in San Francisco, CA, from July26th to July 30th, to learn more about Ascent PBV and see a demonstration.
About Real Intent
Real Intent is the innovator of automating the intelligence of formal techniques for design verification. This technology is being used to solve critical problems encountered by design and verification teams worldwide. Real Intent's family of products dramatically improves the functional verification efficiency of leading edge ASICs and FPGAs devices.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: +1 (408) 830-0700 fax: +1 (408) 737-1962, Web: www.realintent.com, e-mail: Email Contact, Twitter: RealIntent.
Ascent, Meridian and PureTime are trademarks of Real Intent, Inc.
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Real Intent Press Contacts Carol Hallett VP of Worldwide Sales and Marketing +1-408-830-9303 Email Contact Georgia Marszalek ValleyPR LLC for Real Intent +1-650-345-7477 Email Contact