The RF platform is supported by an RF PDK specifically for the 65nm LPe process. The kit significantly reduces design time and helps ensure first-time-right silicon for full-featured SoCs with integrated RF. It has been characterized and silicon-validated on the process on Chartered-manufactured silicon, and uses proven techniques from IBM to achieve a high degree of model-to-silicon accuracy. The PDK enables a more flexible methodology, based on a unique parameterized cell (p-cell) design approach that allows designers to tune RF components in a wide variety of ways.
The comprehensive PDK consists of a full palette of transistors and passives, including high fT RF transistors, vertical native (VNCAPs) and MIM capacitors, large tuning range MOS varactors, high Q-factor shielded inductor, precision poly resistors, and RF ESD devices. These device solutions are complemented by RF-centric p-cells, an inductor synthesis kit, EM simulators setup files support and substrate noise analysis kit.
Single-Chip RF Solution
As consumer multi-media mobile applications continue to expand in features and functionality, integrated high-speed wired and wireless connectivity have become essential. Combining high-speed wired and RF subsystems on a single SoC has been a challenge for most companies, historically forcing them to use the less favorable option of multiple-chip solutions that compromise cost and end-product form factor. The RF platform from Chartered is intended to reduce the time, cost and risk associated with developing single-chip solutions that incorporate RF by making the latest process technology more accessible for those applications.
“The IBM Joint Development Alliance, known primarily for its advanced CMOS process technology development, has now added derivative technology development to the collaboration portfolio,” said Scottie Ginn, vice president of Design Enablement and Packaging, IBM Semiconductor Research and Development Center. “We have invested heavily in developing a methodology that ensures the highest level of accuracy in RF design. Chartered has leveraged this RF methodology for its 65nm process to realize the full potential of the underlying process technology.”
In addition, a wide spectrum of IP support for RF applications is available for the 65nm RF platform. This includes silicon tested RF subsystems for WiFi, WiMax, and GPS; a host of industry standard interfaces (mDDR/DDR/DDR2, USB 2.0, PCI express, SATA II, and LVDS); and functional analog /mixed signal subsystems (Analog Front End, Audio CODEC, Video ADC/DAC, PLL/DLL, and baseband DAC/ADC). Through Chartered’s participation in and support of the WISPA consortium, the 65nm RF process is backed by leading RF and SoC design services companies that can facilitate IP customization and software development via reference boards. WISPA participants Socle Technology Corporation and Catena have worked together to develop a modular platform consisting of RF and baseband functions centered on hardened ARM9 and ARM11 microprocessor cores.
“By using the Chartered 65nm RF platform and RF PDK, all our silicon test chip measurements correlate extremely well with the simulation and we are able to achieve good progress with the system design in a very short time and with high confidence of getting the expected result. We believe that wireless connectivity will be commonplace in the mobile market and our goal is to make the integration of those wireless subsystems as accessible as possible so that product companies can focus on other phases of the hardware and software solution,” said Kave Kianush, CTO and vice president at Catena.
“Close collaboration with our partners and industry specialists in the RF and wireless ecosystem is essential to being able to offer a robust solution that addresses the needs of leading-edge mobile and wireless product developers. Combined with their specific capabilities and technology, our underlying process technology makes an ideal foundation for a market-ready integrated SoC platform. The silicon-verified mixed-signal/RF PDK serves to facilitate analog, mixed-signal and RF designs, RF SoC integration and verification,” said Dr. Shao-Fu “Sanford” Chu, vice president of device technology division, technology development at Chartered.
Enhanced 65nm Low-Power Process
Chartered’s enhanced 65nm low-power process (65nm LPe) features multi-voltage threshold options for optimizing power and performance, and 4-9 metal layers to optimize die size requirements. It offers support for a rich portfolio of RF and analog components, and is supported by a robust ecosystem of EDA tools and IP blocks, including a broad offering of standard cell and IO libraries from leading suppliers.
“The types of wireless-enabled products being developed by our mutual
customers require a high level of IP integration to support the growing
feature sets requested by consumers. Chartered’s enhanced 65nm low-power
technology delivers unique advantages by providing market-leading
leakage benefits and support for a wide portfolio of proven IPs for SoC
integration. Socle’s expertise in ARM9 and ARM11 integration leverages
the ecosystem supported on Chartered’s 65nm LPe platform and allows
efficient customization of the feature set requested by a customer to
bring its products to market faster and at lower risk,” said Chou-Te
Kang, vice president of R&D at Socle.