Toshiba and its technology partner, SanDisk, unveiled these key technology advances today at the International Solid State Circuits Conference (ISSCC) now underway in San Francisco, California.
Manufacturers of NAND flash memories must respond to demand for higher density with lower costs. Toshiba and SanDisk have done so through the application of its innovative technologies.
The 3-bit-per-cell 32nm generation device uses optimized circuit design for the row decoder and extended column architecture, which significantly contributed to a 113mm2 chip, the smallest die size yet achieved in this generation. The 4-bit-per cell applies super multi-bit programming technologies, which realizes 64Gb without increase in chip size, while achieving a write speed performance of 7.8MB/s.
Toshiba and SanDisk have maintained their continuing leadership in the development and manufacturing of advanced NAND flash memory. Toshiba will promote further development in leading-edge process technologies to further widen the scope of application and to expand the NAND flash memory market.
Kaori Hiraki, +81-3-3457-2105
Corporate Communications Office