Calypto to Demonstrate Power Optimization, Functional Verification Products at CDNLive! Silicon Valley Designer Expo

SANTA CLARA, Calif.—(BUSINESS WIRE)—September 4, 2008— Calypto Design Systems Inc., the leader in sequential analysis technology, will demonstrate PowerPro CG (clock gating) and SLEC (sequential logic equivalence checker) Wednesday, September 10, at the Designer Expo (Booth #60) during CDNLive! Silicon Valley 2008 at the San Jose Convention Center in San Jose, Calif.

Additionally, Calypto will present, A verifiable path from system-level to register transfer level (RTL) implementation using Sequential Logic Equivalence Checking, as part of the Cadence System Level Design Techtorial. This half-day techtorial titled, Advanced methodologies, flows and best practices for SoC IP design and verification using high level synthesis (HLS) with C-to-Silicon Compiler, will be held Tuesday, September 9.

For more details on Calypto, visit:

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About Calypto

Founded in 2002, Calypto Design Systems, Inc. empowers designers to create high-quality, low-power electronic systems by providing best-in-class power optimization and functional verification software, based on its patented sequential analysis technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. More information can be found at:

Calypto, PowerPro, SLEC and Enabling ESL are trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.


Public Relations for Calypto Design Systems
Nanette Collins, 617-437-1822
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