edXact (Voiron, France) provides software solutions that help semiconductor designers to remove the backend verification bottleneck, while maintaining their existing design flow and achieving tape-out accuracy. Through the in-Sync program, edXact has access to Synopsys’ timing analysis and fastspice tools, as well as its parasitic extraction toolset, to establish and test a smooth interoperable design flow between Jivaro™ and Synopsys’ products for the benefit of its mutual customers.
“We recognize that designers don’t have the time to fix interoperability problems between software tools,” said Karen Bartleson, sr. director of Interoperability Programs at Synopsys. “in-Sync establishes relationships with EDA vendors in order to facilitate this interoperability.”
“We are excited to be part of the in-Sync program,” said Mathias Silvant, edXact President. “This means that a number of customers who are demanding or using the proposed flows will benefit from our collaboration.”
Founded in 2004, edXact SA focuses on electronic design tools aimed at physical verification tasks. edXact’s innovative model order reduction technology helps accelerate extensive backend verifications in complex IC design cycles. edXact’s headquarters are based in Grenoble area, France.
For additional information: http://www.edxact.com