Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification Methodologies

We are excited to present our latest breakthrough innovations in SoC Design & Verification at DAC 2018. Together with our product and technology experts, we will demonstrate cutting-edge verification methodologies in the areas of Emulation and Prototyping, Mixed-Signal and Mixed-Language Simulation, Machine Learning, High-Performance Computing, Static Design Verification and Embedded Vision for Automotive.

 

Technical Sessions and Demos

June 25-27, 2018 from 10:00 AM to 6:00 PM @ Booth #2628

How to Register: Email us at marcom@aldec.com with the following information (Presentation Title, Full Name, Company Name, Date and Time).

The following presentations will be offered continuously at the Aldec booth throughout the day. Don’t forget to visit our coffee bar while you’re there!

 

Presentation Track 01: Single Platform for ASIC/SoC Emulation and Prototyping

  • Partitioning Design for Multi-FPGA Prototyping
  • Hardware-Software Co-debugging Using Hybrid QEMU/HES-DVM Co-emulation
  • In-Circuit Emulation (ICE) of today’s SoCs

Presentation Track 02: Mixed-Signal and Mixed-Language Simulation Solutions

  • Aldec and Silvaco Mixed-Signal Simulation
  • SoC Simulation Environment for Mixed-Signal Designs
  • Simulation Environment for HLS Designs
  • What’s New in VHDL 2018 and Open-Source Verification Methodology?
  • Why do we need UVM Register Abstraction Layer?

Presentation Track 03: Static Design Verification Methodologies           

  • Static Verification for FPGAs
  • Finite State Machine Exploration and Checking
  • Reset and Reset Domain Crossing Analysis
  • Boosting Productivity with Unit Linting

Presentation Track 04: Machine Learning, High Performance Computing & Embedded Vision

  • Solving a Sudoku Game with BinCNN
  • FPGA-based Implementation of ADAS Bird’s Eye View (Embedded Vision)
  • Re-configurable Accelerators for HPC Applications
  • Genome Short Reads Alignment

Presentation Track 05: Traceability and Reusability for Safety Critical Projects

  • From Traceability to Reusability
  • Generating DO-254 compliant documents for FPGA projects
Aldec LogoAldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Embedded, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.



Review Article Be the first to review this article
Aldec

ClioSoft at DAC

Featured Video
Jobs
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
Symposium on Counterfeit Parts and Materials 2018 at College Park Marriott Hotel & Conference Center MD - Jun 26 - 28, 2018
Concar Expo 2018 at Convention Hall II Sonnenallee 225 Berlin Germany - Jun 27 - 28, 2018
Nanotech 2019 at Tokyo Big Sight East Halls 4-6 & Conference Tower Tokyo Japan - Jun 30 - 1, 2018
INMMiC 2018 at university campus of Brive La Gaillarde France - Jul 5 - 6, 2018
ClioSoft at DAC
Altair
TrueCircuits: IoTPLL



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise