Dolphin Integration augments the TSMC IP Ecosystem at 40 nm ULP eFlash with new TITAN Read Only Memory

Grenoble, France - April 09, 2018 - Dolphin Integration, leader in innovative design solutions for the next generation of Energy-Efficient System-on-Chips, augments TSMC’s IP ecosystem at 40 nm with TITAN, a breakthrough architecture for Read Only Memory compiler. This cost effective, single-layer and late programmable ROM compiler is capable of generating instance sizes from 512 bits to 1 Mbits. It is immediately available for evaluation on  your private space, MyDolphin.

This  40 nm ULP eFlash ROM compiler, based on the TITAN architecture, combines high-density with ultra-low power consumption. This innovative architecture has already been silicon proven in 55 nm and 90 nm process technologies. The TITAN ROM compiler reduces fabrication costs and time-to-market as programming is performed using only the metal 1 layer. Configurable multiplexer option, from 8 to 128, provides designers with the flexibility to select a ROM configuration to meet the target performances with the optimal floorplan. The online ROM compiler allows the designer to quickly complete an objective performance assessment. It automatically generates datasheets, simulation (Verilog), layout (GDSII), footprint (LEF), timing/power (Liberty) and MBIST (Tessent) models.

“There are a number of applications which still embed a large amount of ROMs to store the application program, be it Low Energy Bluetooth, BT audio, etc.,” said Frédéric Masson, Business Unit Manager at Dolphin Integration. “The superior density of our sROMet, which is known for enabling up to 35% area savings, partakes in ensuring the best competitive advantage in such cost-sensitive applications!”

To enable the cost-effective design of energy-efficient SoCs, Dolphin Integration is expanding its  portfolio of foundation IPs at TSMC 40 nm to complement their existing offering of Power Fabric IPs. Complementary to this ROM compiler, a new generation of dense and low-power SRAM memory compilers (Single-port RAM TELESTO and Dual-port RAM ERA) is under completion as well as a standard-cell library (SESAME BiV) dedicated to always-on power domains.




Review Article Be the first to review this article
Aldec

Downstream : Solutuions for Post processing PCB Designs

Featured Video
Jobs
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Director, Business Development for Kongsberg Geospatial at remote from home, Any State in the USA
Director, Business Development for Kongsberg Geospatial at Ottawa, Canada
Upcoming Events
IPC Technical Education - PCB Layout - Place and Route at Del Mar Fairgrounds 2260 Jimmy Durante Blvd. Del Mar CA - May 2, 2018
IPC Technical Education at Wisconsin Center 400 W Wisconsin Ave. Milwaukee WI - May 8, 2018
IPC High Reliability Forum at Embassy Suites: Baltimore-At BWI Airport 1300 Concourse Drive Linthicum MD - May 15 - 17, 2018
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL
DAC2018



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise