- Advanced layout methodologies and simulation-driven layout improve layout productivity by up to 50%
- Reduces FinFET layout effort by >3X
- Improves Virtuoso ADE simulation throughput by up to 3X
- Reduces design variation analysis time by approximately 20% using advanced statistical algorithms
- Virtuoso ADE Verifier improves path to standards compliance by approximately 30%
- Enhanced Virtuoso System Design Platform with multi-technology and multi-PDK support
SAN JOSE, Calif. — (BUSINESS WIRE) — April 10, 2018 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced major enhancements to its Cadence® Virtuoso® custom IC design platform that improve electronic system and IC design productivity. The enhancements affect almost every Virtuoso product, providing system engineers with a robust environment and ecosystem to design, implement and analyze complex chips, packages, boards and systems.
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For more information on the new Virtuoso platform, please see www.cadence.com/go/virtuoso-whats-new.
Enhanced Virtuoso System Design Platform
Some of the most important enhancements in the 2018 Virtuoso platform improve the capabilities of the award-winning Virtuoso System Design Platform introduced last year. The updated Virtuoso System Design Platform now allows system engineers to seamlessly edit and analyze the most complex heterogeneous systems. It enables package, photonics, IC analog and RF engineers to work through a single platform and utilize the full breadth of the Virtuoso platform’s most trusted set of design applications.
In the heart of the new system design environment is a set of technologies that enable simultaneous edits across multiple process design kits and technologies. The platform also provides seamless interoperability with Cadence SiP Layout and the Sigrity™ analysis technology portfolio for a comprehensive chip-to-board toolset.
Virtuoso Advanced-Node Design and Layout
In this release of the Virtuoso platform, Cadence incorporated innovative advanced-node methodologies that speed the designs done in process technologies from 22nm down to 5nm. By collaborating with leading-edge foundries, ecosystem partners and customers, Cadence developed advanced technologies that automatically manage process complexities with innovative methodologies that allow engineers to focus on their design intent. In circuit design and analysis, advanced statistical algorithms specifically targeting FinFET designs uncover circuit variances early, reducing design variation analysis time by approximately 20% using advanced statistical algorithms.
In layout design, a unique multi-grid system abstracts complex design rules of the latest 7nm and 5nm processes, while allowing engineers to increase their use of placement and routing technologies to significantly increase layout design productivity. Using these techniques with the enhancements made to the advanced methodology reduces layout effort by >3X in 7nm production designs.
Virtuoso Advanced Design Methodologies and Automation
Cadence made several enhancements to improve analog design and analysis. The Virtuoso Analog Design Environment (ADE) simulation throughput is improved by up to 3x due to enhanced integration with the Cadence Spectre® Circuit Simulator, increasing simulation throughput and using advanced analysis to reduce design iterations. Unique capabilities were added to the Virtuoso ADE Verifier to centralize cross-domain electrical specifications so the path to standards compliance (e.g., ISO 26262) is streamlined by approximately 30 percent.
The Virtuoso Layout environment is evolving from an electrically aware layout to the industry’s first electrically and simulation-driven layout using unique sets of in-design technologies to ensure circuit integrity and performance. This new simulation-driven layout addresses many of the electromigration (EM) and parasitic challenges of critical circuits and advanced-node designs. To increase layout automation, the new environment introduces breakthrough techniques for hierarchical floorplanning and planning along with new placement and routing automation technologies to increase layout design productivity and throughput and to shorten layout turnaround time.
With the complexity of today’s chips, one of the big challenges is dividing layout tasks among the design team. The Virtuoso platform now features an innovative concurrent real-time team design editing capability, allowing teams to distribute layout tasks and perform what-if explorations. This is particularly useful for design-rule check (DRC) fixing, chip finishing and manual routing.
Cadence estimates that the new innovative layout environment with electrically driven routing and wire editing, real-time design editing and revolutionary design planning techniques improves productivity by up to 50 percent.
“At Bosch, we design mission-critical systems where high reliability is
our paramount concern. We need EDA tools that provide our engineering
community with the ability to efficiently design, analyze and layout
circuits that meet our reliability constraints while not dragging down
overall designer productivity,” said Göran Jerke, EDA senior project
manager, Bosch. “Our longtime collaboration with Cadence has led to
crucial innovations in both electrically-aware and now the new
electrically-driven layout design.”