Gen-Z Consortium Announces the Public Release of Its Core Specification 1.0

Gen-Z Core Specification 1.0 Enables Silicon Development

BEAVERTON, Ore. — (BUSINESS WIRE) — February 13, 2018The Gen-Z Consortium, an organization developing an open standard interconnect designed to provide high-speed, low latency, memory-semantic access to data and devices, today shared the Gen-Z Core Specification 1.0 is publicly available on its website.

The Gen-Z Core Specification 1.0 enables silicon providers and IP developers to begin the development of products enabling Gen-Z technology solutions. Gen-Z's memory-centric standards-based approach focuses on providing an Open, reliable, flexible, secure, and high performance architecture for housing and analyzing the incredible amount of information at the edge coming into the data center.

“Our membership has grown significantly throughout 2017, now totaling more than fifty members, and we are proud of the hard work that has culminated with the release of our first Core Specification,” said Gen-Z President, Kurtis Bowman. “We anticipate great things in 2018 as silicon developers begin implementing Gen-Z technology into their offerings and the ecosystem continues to grow.”

Gen-Z technology supports a wide range of new storage class memory media and acceleration devices, features new hybrid and memory-centric computing technologies, and uses a highly efficient, performance-optimized solution stack. Its memory media independence and high bandwidth coupled with low latency enables advanced workloads and technologies for end-to-end secure connectivity from node level to rack scale.

Learn more and download the Gen-Z Core Specification 1.0 on our website.

Supporting Resources:

About Gen-Z Consortium

Gen-Z is an open systems interconnect designed to provide memory semantic access to data and devices via direct-attached, switched or fabric topologies. The Gen-Z Consortium is made up of leading computer industry companies dedicated to creating and commercializing a new data access technology. The Consortium’s 12 initial members were: AMD, ARM, Broadcom, Cray, Dell EMC, Hewlett Packard Enterprise, Huawei, IDT, Micron, Samsung, SK hynix, and Xilinx with that list expanding as reflected on our Member List.

The Gen-Z Consortium strongly believes in developing an open ecosystem where members, the broader industry, and customers can work together to deliver robust, high-quality specifications that meet solution needs. The Gen-Z Consortium will periodically publicly post draft specifications and technical concepts to elicit input from the broader industry and directly from customers. For more information visit www.genzconsortium.org.

Member Company Quotes

Alpha Data Inc.

“The release of the Gen-Z Core Specification signals a new phase in bringing high-bandwidth memory-centric technology to reality. Alpha Data has been a member of the Gen-Z Consortium since 2016 and our Xilinx based FPGA boards have enabled multiple demonstrations of high performance Gen-Z technology. With the release of the 1.0 specification, we expect to see many new developments that significantly benefit from this interconnected memory-centric architecture.” – Adam Smith, CEO Alpha Data Inc.

AMD

“AMD joins the other members of the Gen-Z Consortium in celebrating the release of the Gen-Z Gen 1.0 open standard for high-performance, cross platform interconnect technology. Low-latency access to memory and storage in the datacenter is an area of pressing need for open ecosystems and technology development. With this significant step, Gen-Z has defined an advanced, modern protocol designed to deliver a high-performance, cross-platform solution.” – Forrest Norrod, senior vice president and general manager, Datacenter and Embedded Systems Group, AMD

Arm

“Today’s hyperconnected world demands new levels of performance and scalability to analyze and process vast amounts of data in real-time. Open standards, such as Gen-Z, are key to delivering the compute and storage infrastructure solutions required to address this challenge.” – Drew Henry, senior vice president and general manager, Infrastructure Business Unit, Arm

Avery

“The release of the Gen-Z Consortium’s core specification V1.0 is a major milestone for enabling new innovation for in the compute and IT market segments. Avery is well positioned with its expertise in verification IP (VIP) to meet the needs and development efforts based on the 1.0 specification. Avery will be providing the Gen-Z development ecosystem with SystemVerilog/UVM models, functional test suites, and protocol checking to support new IP and silicon design starts in Q1 2018.” – Chris Browy, vice president of sales and marketing at Avery

1 | 2 | 3  Next Page »



Review Article Be the first to review this article
Aldec

Featured Video
Jobs
ASIC Hardware Engineer for BAE Systems Intelligence & Security at Arlington, VA
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, CA
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, PA
Applications Engineer for intersil at Palm Bay, FL
Upcoming Events
IPC APEX EXPO 2018 at San Diego Convention Center San Diego CA - Feb 24 - 1, 2018
DVCon US 2018 at Double Tree Hotel San Jose CA - Feb 26 - 1, 2018
5th EAI International Conference on Big data and Cloud Computing Challenges at Vandalur, Kelambakkam high road chennai Tamil Nadu India - Mar 8 - 9, 2018
DownStream: Solutions for Post Processing PCB Designs



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise