as published in www.eetimes.com, 12 Jan 2012
When Verific started providing (System)Verilog and VHDL parsers in 2001, EDA companies were quick to jump on the bandwagon. Semiconductor companies with internal CAD teams and FPGA companies supporting customer design tools followed suit when they realized that they would be better off re-using Verific's parsers than build their own.
In 2012, we believe that more and more semiconductor and system design houses will do the same and start building one-of-a-kind EDA tools specific to their environment and design practices. With the recent addition of a Perl API to Verific's SystemVerilog and VHDL front-ends, everybody can now have access to an IEEE-compliant parser with no C++ knowledge required. Building your own SystemVerilog design gadget has never been easier and will become a trend in 2012.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.