MONROVIA, California – September 26, 2011 -- Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), is holding a free webinar on how to use the company’s L-Edit physical design tool to reduce the unpredictable costs and workload related to a tapeout deadline. A complete hierarchical physical layout editor that includes fast rendering and all-angle and curved polygons, L-Edit helps engineers reach peak efficiency for design layout.
What: Demonstration of L-Edit, including:
- How to take full advantage of L-Edit’s optimized editing, which allows layout editing with fewer mouse clicks than any other layout editor, for maximum efficiency.
- How to speed up design cycles with built-in productivity tools such as object snapping, alignment tools, automatic guard ring generation, complex Boolean operations on objects or layers, and cross-probing between schematic and layout.
- Support for parameterized cells, which allows creation of automatic custom layout generators (or use HiPer DevGen to easily set up layout generators for most common devices such as MOSFETs, resistors, or capacitors).
- Built-in interactive DRC, which displays violations in real time while editing, helping to create compact, error-free layouts the first time.
- Node highlighting capability, which allows highlighting of all geometry connected to a node so that LVS problems such as shorts and opens can be quickly found and fixed.
When : On demand
For additional product information, whitepapers, data sheets, and on-demand webinars and demonstrations of other Tanner EDA products, please visit Tanner EDA’s Videos & Demos homepage
About Tanner EDA
Tanner EDA provides a complete line of software solutions that drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.
Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.
HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc.
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