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Title : Reduce Verification Complexity in Low/Multi-Power Designs
Company : Mentor Graphics
Date : 16-Sep-2013
Downloads : 656

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Verification requirements are growing in all market segments. Ensuring these requirements are met requires design verification that goes beyond traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are affected by these requirements, while both system-on-chip (SoC) and full custom designs also need comprehensive reliability coverage.
Learn how Calibre PERC can help you:
  • Understand the interactions between different power domains
  • Ensure signals and voltage domains are protected for all operating conditions
  • Get easy-to-use, unambiguous debug results without exhaustive test vectors
  • User Reviews More Reviews Review This File

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