All Categories : Technical Papers Bookmark and Share

Title : Reduce Verification Complexity in Low/Multi-Power Designs
Company : Mentor Graphics
Date : 16-Sep-2013
Downloads : 659



If download does not start, click here.
Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

Verification requirements are growing in all market segments. Ensuring these requirements are met requires design verification that goes beyond traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are affected by these requirements, while both system-on-chip (SoC) and full custom designs also need comprehensive reliability coverage.
Learn how Calibre PERC can help you:
  • Understand the interactions between different power domains
  • Ensure signals and voltage domains are protected for all operating conditions
  • Get easy-to-use, unambiguous debug results without exhaustive test vectors
  • User Reviews More Reviews Review This File
Aldec

ClioSoft at DAC

Featured Video
Jobs
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
2018 FLEX Korea at Room 402/ 403, COEX Seoul Korea (South) - Jun 20 - 21, 2018
INTERSOLAR EUROPE 2018 at Munich Germany - Jun 20 - 22, 2018
DAC 2018 at Moscone Center West San Francisco CA - Jun 24 - 28, 2018
Symposium on Counterfeit Parts and Materials 2018 at College Park Marriott Hotel & Conference Center MD - Jun 26 - 28, 2018
ClioSoft at DAC
Altair
TrueCircuits: IoTPLL



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise