All Categories : Technical Papers Bookmark and Share

Title : STIL Verifier: Post-Silicon Functional Test Automation within Cadence Incisive
Company : Globetech Solutions
Date : 26-Jul-2011
Downloads : 3

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

Earlier this year, Globetech Solutions announced STIL Verifier, the industry’s fastest route from functional verification to functional silicon test and debug. STIL Verifier aims at extending verification capabilities into the post-silicon validation domain. Its goal is also to leverage verification environment constructs, process data, and design knowledge to increase effectiveness and reduce cost during debug, validation, and volume test of semiconductor devices.
User Reviews More Reviews Review This File
Looking at STIL - stevebr - Report As Inappropriate

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Applications Engineer for intersil at Palm Bay, Florida
Design Verification Engineer for intersil at Morrisville, North Carolina
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise