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Posts Tagged ‘SLEC’

Calypto’s Triple Threat: HLS, Equivalence checking, Power

Saturday, March 24th, 2012

 

When we last left our hero – that is, Mentor’s Catapult C high-level synthesis tool –  it had just been sold off to Calypto in a move that the companies said, “will create a better integrated ESL hardware realization flow.”

Now, some 7 months into the adventure, I spoke with Calypto’s recently appointed VP of Marketing Shawn McCloud at DVCon:

Shawn: Calypto specializes in the ESL hardware implementation flow. We’re accelerating design with Catapult, optimizing the design for power efficiency with PowerPro, and doing verification with SLEC, which provides equivalence checking from RTL-to-RTL, or from C-to-RTL.

Q: Who’s the competition?

Shawn: Nobody has all 3 of these products, but within high-level synthesis, it’s Forte – and yes, we are the new Mentor. For power, the competition is Apache and Atrenta, but they’re both manual solutions, while we’re automated. And, nobody has our equivalence checking capability.

Q: Your exit strategy?

Shawn: Our goal is to grow 25-to-30%, year over year, and then we will have a number of different options: acquisition, or even an IPO.

(more…)




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