Posts Tagged ‘NXP’
Thursday, May 12th, 2016
Aachen-based Silexica is making waves in the world of multi-core and embedded systems, as evidenced by their recent win in the German Silicon Valley Accelerator program. Company leadership was motivated to spend Q1_2016 in Silicon Valley, networking and meeting with thought leaders in the Bay Area’s tech community.
While he was in California, I had a chance to speak by phone Silexica CEO Max Odendahl. As many know, the problem of parsing code to take advantage of multi-core systems is a massively tough one to solve, one of the Grand Challenges in computing. My conversation with Odendahl was compelling, because it would appear his company has the solution.
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Tags: Altera, ARM, Cadence, Ericcson, German Silicon Valley Accelerator, Max Odendahl, Movidius, NVIDIA, NXP, RWTH Aachen University, Silexica, Synopsys, TI
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Thursday, March 17th, 2016
Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.
After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.
I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?
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Tags: Accellera, Accellera PSWG, Agnisys, AMD, AMIQ EDA, Analog Devices, Breker Verification Systems, Cadence, Cisco, DVCon, Faris Khundakjie, IBM, Intel, Mentor Graphics, NVIDIA, NXP, Portable Stimulus Working Group, Qualcomm, Semifore, Synopsys, Tom Anderson, Tom Fitzpatrick, Vayavya Labs
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Monday, March 23rd, 2015
The last time I spoke at length with OneSpin’s Dave Kelf, the conversation was all about the Cloud. This week we picked up where we left off, talking about the Cloud, but then moved on to the Wild West. Dave is quite taken with the idea that the current situation in EDA is on par with the Wild West, that mythical place where a lack of structure and entrenched establishment allows true innovators to run wild free. First however, we caught up with OneSpin and the Cloud.
Dave said, “These days, engineers cannot afford to stick their necks out. Neither their managers nor their corporate leadership want to take risks, and the engineers know it. Although engineers realize moving design to the Cloud makes sense, when they try to explain that to their bosses or corporate lawyers it often leads to legal discussions around the problems of having [propriety] IP leave the company’s server.
“At OneSpin, however, we are able to eliminate these issues by generating abstract verification proof problems that go to the Cloud for computation without the transfer of IP or even [identifiable markers], assuring our customers that the process is very secure. Moving to the Cloud means design teams will have access to infinite computing, with huge verification jobs running simultaneously.”
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Tags: Amazon, Assertion-Based Formal Verification, Broadcom, Cadence, Dave Kelf, Fujitsu, GlobalFoundries, Google, high-level synthesis, Intel, Microsoft, NXP, OneSpin, OneSpin 360 DV-Inspect, OneSpin 360 DV-Verify, Qualcomm, Raik Brinkmann, Samsung, Silicon Cloud, Sony, Synopsys, SystemC, TSMC
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Thursday, July 17th, 2014
Once again EDAC’s Market Statistics Service has released quarterly results for the EDA and IP industries, and once again Mentor Graphics CEO Wally Rhines has taken time to debrief the press on the numbers. When we spoke by phone on July 15th, Rhines started with a qualitative eval of the financial situation in Q1_2014, and moved from there to answer several longer-range questions about autos and today’s troubled world.
“The first quarter of 2014 was good for the industry, but not great,” he said. “With overall growth of 4.6 percent, year over year, it was a good quarter with the highlight being logic design was up a solid 6.6 percent. Other than that, there was not a lot else [remarkable in EDA].”
“Steady, but not glamorous, for Q1?” I asked.
Rhines said, “Yes, steady as she goes in EDA. The IP business, however, was up strongly in Q1, driven up by results from the non-reporting companies, not members of EDAC. We collect public info from non-reporting IP companies such as ARM, Imagination Technologies, MIPS, Rambus [and Synopsys], and we can see overall that the IP business [exhibited] 10-percent growth, quarter over quarter, Q1_2013 to Q1_2014.”
He added, “The bigger trend [visible in] the current MSS report is that all of the world is showing strong [sales], except Japan which is very weak, down 19 percent in contrast to Asia Pacific, which is up 13.5 percent.
“You should also note that North America and Europe are quite strong, up 7 percent or more. Japan is well below those regions as well. Japan used to be a big part of the total [numbers for the industry], substantially larger than the Asia Pacific Region, but now the Pac Rim is twice the size of the Japanese market.”
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Tags: ARM, Cadence, DAC, EDAC, Egypt, El Salvador, Ford, Imagination Technologies, Infineon, Israel, James Buczkowski, MathWorks, Mentor Graphics, Microsoft, MIPS, MSS, Nokia, NXP, Pakistan, Rambus, Renesas Electronics, Synopsys, TI, Wally Rhines
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