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Posts Tagged ‘Cadence’

Silicon Cloud: Architecting the Future of Design

Wednesday, July 16th, 2014


Despite its ethereal-sounding name, Silicon Cloud International is a company grounded in the reality of chip design, particularly for an important international demographic, professors and students. Mojy Chian is CEO of the Singapore-based SCI. We spoke recently by phone.

Chian started by defining the cloud. “The concept of the cloud is straightforward. It means remote computing, so if you are not using your local machine, you are using the cloud. There are a lot of applications in the cloud, including eCommerce, Facebook, cloud storage, and remote collaboration based in the cloud.

“Certainly, usage of the cloud has taken off in recent years, but remember there are several different types of clouds. In contrast to private cloud computing, public cloud computing means accessing machines [owned by other companies such as Amazon], where you can actually go and use their machines.”

Our conversation being specific to chip design, I asked Chian to comment on widespread industry concerns regarding security when working in the public cloud. Companies are oft-times reluctant to compute and/or store their designs in the public cloud for fear of losing their precious data to hackers and pirates.


DAC 2014: Algorithms, Adjacencies, Animosities, World Peace

Thursday, June 5th, 2014


The June breezes were intense in San Francisco this week. The fog was swirling out at the Great Highway, and making itself known across town amidst the flags flying sharply over Moscone Center. The Electronic Design Automation and IP communities were out in force in and around South Hall, while thousands of edgy app developers were playing out their own dramas across the street and down the block in and around West Hall where Apple was holding court at the same time. Fourth and Howard was awash all week in hordes and gaggles of the people who are shaping the future of the world.

Algorithms – Perhaps as never before, algorithms were the number one topic at DAC this year, and in so many different shapes and sizes. Algorithms for high-level synthesis, algorithms for creating models, algorithms for translating physical data into guidelines for design, algorithms for translating assertions into verification metrics for more orderly validations, algorithms for encrypting and decoding, algorithms for compression and decompression, algorithms for converting approximate computational output into exactitude, algorithms for hearing, seeing, and even believing. In San Francisco this week at DAC, it was algorithms all the way down, everywhere you looked.

Adjacencies – The Design Automation Conference is all about ideas, and this year the principle idea was change. The Executive Committee re-shuffled the long-standing deck of cards that’s represented the most important topics at DAC over the last 50 years and came up instead with a whole new set of talking points.


Phoenix Rising: Gary Smith at DAC

Thursday, May 29th, 2014


Like a phoenix rising from too-early reports of a reduced participation in life, the legendary Gary Smith has created a schedule of appearances at the 51st Design Automation Conference in San Francisco that would fell a man half his age. Every time you turn around at Moscone Center next week, or the Intercontinental Hotel before that, you’ll be face-to-face with events featuring the Guru Extraordinaire of EDA.

Sunday evening from 5:00 pm to 5:30 pm, Gary will yet again ring the opening bell at DAC, this year in Ballroom A of the Intercontinental Hotel across the street from Moscone. I’m putting good money on a bet that Gary will be on stage there in his best Tropical Whites, accompanied by slides, predictions, and previews of the Next Epoch in EDA and his Pavilion Panel the next day.


OneSpin: A must see at DAC

Wednesday, May 14th, 2014


There are three reasons you should visit OneSpin at DAC in San Francisco. First, they’re a German company, albeit with a group in California, so it’s great to chat with the German contingent while they’re in town; second, it’s been 10 years since they were spun out of Infineon, so they have that much experience selling verification tools into some of the largest semis in the world; and third, Dave Kelf heads up marketing for the company and any conversation with Dave’s going to leave you better informed and happy to be working in the industry. He’s the ultimate optimist.

I spoke by phone recently with Dave. It was morning in Silicon Valley and late afternoon in the U.K. as he described a new tool recently released by OneSpin that’s useful for evaluating verification coverage.

Dave said, “OneSpin’s been working on this for a while with customers. It was actually a customer who said to us: Look, you’ve got this great coverage engine. Why don’t you release it as a separate tool, because it could be very beneficial.

“So we looked at our coverage engine, added some features, made it useful to a number of different companies, and released it as Quantify. The response has been great. It’s really started to transform the environment for our customers, a group of very high-end companies.”


May Day: EDA in Moscow

Thursday, May 1st, 2014


A friend likes to spend hours on Sundays reading the New York Times cover to cover. Pointing to an article from last weekend’s edition, he exclaimed, “This Putin guy is a real piece of work! He’s a total dictator and worse, thinks he can win the world war he’s about to unleash!”

“Stay calm and carry on,” I said soothingly. “It’s a global economy these days and he will succumb to the pressures of maintaining a steady environment for international trade.”

“Yeah?” the friend scoffed. “And you call yourself a student of history? You don’t think there was a global economy in 1939?”

“Look,” I said. “Seriously. The EDA industry is in Moscow. Do you think they’d be playing in an environment that’s spiraling out of control?”

“Yeah?” he retorted. “The world, starting with Putin, doesn’t care about your precious EDA. And besides, who says EDA’s in Moscow?”


M&A: It’s Jasper to Cadence, at last …

Monday, April 21st, 2014


In the moments prior to Cadence’s quarterly earnings call this afternoon, the company released news of the acquisition of Jasper Design Automation for $170 million, less $24 million in cash, and a small tremor rippled out across the EDA Nation.

Paraphrasing Cadence CEO Lip-Bu Tan in the early minutes of his 5pm ET earnings call: We are very pleased to announce a definitive agreement to acquire Jasper Design Automation. This will help us to further meet our customers’ needs for more advanced verification solutions, particularly today as verification now represents 70% of the cost of SoC development. Together, Cadence and Jasper can move forward, offering the strong formal verification solutions leading customers need. In addition, Cadence is also very pleased to be bringing on board the strong team at Jasper, a team with excellent real-world experience.

All good stuff, yes? So why any tremors in our beloved little EDA Nation?


CDNLive 2014: Delicious Sensory Overload

Wednesday, March 12th, 2014


In the spirit of full disclosure, Cadence paid for lunch yesterday for the Press Corps attending CDNLive 2014. We had a scrumptious gourmet meal at Tosca in the lobby of the Hyatt Regency before returning to the Santa Clara Convention Center next door to have an hour-long “one-on-one” with Cadence CEO Lip-Bu Tan. In truth, it was actually an hour-long “twenty-on-one” with CEO Tan, because all of the usual suspects EDA Press Corps was in the room throwing softball lobbing questions at Tan.

Over the course of the hour, we learned that CEO Tan has a host of different investment partners – sorry, didn’t write down the names – involved in his various VC-funded ventures that span everything from GoPro [the trendy wearable camera enterprise out of Half Moon Bay] to a fabless startup that he said can tape-out a design at 16 nanometers for a scant $15 million, rather than the usual $150 million being lamented today in the global press. [In fact, Tan mentioned so many ventures he’s involved with, it begs the question: How does he have time to run Cadence?]

We learned that CEO Tan is very excited about all of the technologies involved in the semiconductor design/supply chain, that he believes it’s a great time to be a player in the industry, and that Cadence is innovating rapidly on multiple fronts simultaneously. And if/whenever Tan senses that they’re slowing down in any particular area, he pushes Cadence Engineering to move forward even faster.


Incisive vManager: CDN takes on biggest baddest SoCs

Wednesday, February 26th, 2014


How appropriate, the week prior to DVCon, for Cadence to announce a major new verification enhancement – Incisive vManager. Per a phone call last week with Cadence MDV [metric-driven verification] Product Management Director John Brennan, the company has spent the last 4 years working on this new “verification planning and management solution.”

Brennan said, “Incisive vManager has been in customer beta for the past 2 years, so this is actually our third release. Previously we’ve been quiet [about the product], but now we’re ready to say, ‘Come one, come all, and look at what we’ve done!’

“We’ve completely re-engineered and re-invented ourselves regarding verification planning and management – an important area I’ve been working on for over 10 years. What we’ve done with Incisive vManager is to redo our existing solution, both for reasons of scalability and for better addressing the needs of our customers, specifically the increased size and complexity of today’s verification [task] with a new client-based solution for multiple users.


Imperas: Test it now or Recall it later

Thursday, February 20th, 2014


These are good days for virtual prototyping vendor, UK-based Imperas. The company will be making appearances this coming week at Embedded World in Nuremberg, at DVCon in San Jose the following week, and at CDNLive in Santa Clara the week after that, as well as several events in the UK in this same time frame. Imperas has a lot to talk about, including an announcement involving MIPS, a division of Imagination Technologies.

Per CEO Simon Davidmann in a recent phone call: “We’re small, self-funded and growing, with revenues last year up 65 percent. [Even better], the type of customers we’re seeing are tier-one semiconductor and embedded systems companies. We want to help people build better software. No one builds a chip without simulation, and we believe software development should be done like that as well.”

I asked about the competition. Simon answered, “It’s true, other people have models in the same space as ours – companies like Synopsys, Cadence and ARM – but we tend to cooperate with them. Our real competition is legacy breadboards, and kick-it-and-see techniques, rather than proper methodologies.

“For most complex SoCs, many people try to develop software with simulation at the RTL level, or with a hardware-accelerator box, but those approaches don’t get the throughput of software and performance they need. And with a prototype, they don’t get the controllability and observability. That’s why most of our competition is the legacy mindset in the customers.”


D&VCon: A labor of love for Krolikoski & Co.

Thursday, February 13th, 2014


If ever there was a year when you thought to attend DVCon, this should be it, according to a recent phone call with Cadence Fellow Stan Krolikoski, serving as General Chair for the second year in a row. That’s because DVCon 2014 will be serving up the D and the V in equal measure, and won’t be skewed towards the V in DVCon as it has been [perhaps] in the past.

Per Stan, “We’ve gotten feedback every year from attendees that they want more emphasis on design. They say they like verification, but they want more design, so last year I gave marching orders to the Technical Program Committee [headed by Paradigm Works’ Ambar Sarkar] that they should add more people on the review committee who represent design.

“It’s actually been a long time in coming. Although last year was the 25th anniversary of the conference, 10 years ago the name was changed to DVCon. Prior to that, it was HDLCon and the content reflected that name. When the name was changed to DVCon it was supposed to include both design and verification, but [functional verification emerged as the larger focus].”

That focus meant that those types of experts tended to dominate attendance, according to Stan, but that’s been fixed this year: “We will still have excellent functional verification sessions at DVCon – everything for the beginner through to the guru, it’s all there – but we will also have sessions on low-power design, on analog/mixed signal, and on system-level design, as well as IP integration. We’re clearly moving away from just verification in adding lots of design content to the program that’s of interest to our audience.”


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