EDACafe Industry Predictions for 2020 – Imperas

The Lost Art of Microprocessor Verification

Microprocessors have been a disruptive force within the electronics industry since the 1970’s, bringing compute resources to new levels of devices and breaking barriers as innovation based on the key specification of ISA (Instruction Set Architecture), which allows hardware and software to have a defined boundary for successful collaboration. Some well documented market segments solidified around an architecture and the proprietary alternatives were relegated to niche markets or the history books, but the open ISA of RISC‑V is poised to bring a new wave of flexibility with standard and custom extension that allow optimization for end applications. The engineering freedoms, which are now available to SoC developers and system designers, can address the challenges of domain specific devices in the use-cases when the one-size-fits-all approach is not optimal. But to paraphrase a popular Star Trek character, “you cannot break the laws of DV” – if you design it, then you must also complete the test plan before tape-out.

The single source, or closed ISA had the advantage of consolidating the processor verification and test, which in turn became a value-added feature. In the in-house knowledge and experience developed around methodologies and techniques are not typically practiced in the general industry of SoC design. Testing an SoC, which contains a known good IP processor core, is a very different task than verifying the IP core itself.

In 2020, the enthusiasm of system architects looking at the latest configurations of many-core arrays for AI application will also look at the options to extend and optimize the cores themselves.

Processor verification is no longer the remit of the dedicated few, now every semiconductor manufacture or OEM design team can participate. Working together with the EDA suppliers, many will be looking to rethink the methodologies, revisit long held assumptions, and work with both proprietary and open-source tools and solutions. 2020 is not business as usual for processor verification.

Virtual Platforms Announce a Comeback Tour

Many predictions over the past XX (fill in the blanks as necessary) years have predicted that in fact “next” year will be the year that Virtual platforms finally become mainstream, critical, useful and indispensable. The promise of hardware prototypes that can be developed at a pace more common to software projects is understandably appealing. The ability to test and verify software before silicon is available is both a project manager’s schedule saving dream and the inspiration for system a architect’s imagination. But year after year, the simple promise of hardware and software co-design failed to get out of the starting gate. In simple terms, it’s like the childhood puzzle of which came first, the chicken or the egg. System designers working hard to solve a problem and invent the future and just kept working with the business as usual approaches while the virtual platform solution waited for it’s day in the story.

Meanwhile verification engineers found a use-case for adoption with reference models within DV flows for complex designs and processors, which quickly became the norm and kept the focus on accuracy and dependability, a grass roots following that kept the beat alive and focused on quality engineering solutions.

An interesting development in the wave of investment and attention to AI is the system designer’s appreciation that, while cloud-based algorithms are great, they are even better when deployed in dedicated hardware. Perhaps for a datacenter acceleration of some specialist task or as in an edge-based device to avoid communication latency or additional autonomy. From the flexibility of mapping the algorithms to the scalability inherent with cloud-based resources, they see no barrier to approaching the many core compute clusters of AI accelerators. In addition, looking at the options for processing nodes of different capability’s or even optimized with custom instruction. So, they have the large workloads and real-world datasets ready and would really like to see some analysis with some new array-style configurations of processors, and (drum-roll please) flexibility to tune the algorithms to fit the use-case and hardware optimizations. Let’s look back at our notes for a solution for a large software workload, flexibility as hardware and software are configured, and a platform model that can be adapted with near software ease…… Yep it appears to tick all the boxes for a safe prediction 1) Known technology 2) Popular VC funded application 3) Creative use of quality engineering leveraged for popular headline news. 2020 is the comeback year for virtual platform as prototypes (though they never really left).

But it’s not just about the prototypes anymore–yes, that’s the fun and cool part–but the real value in virtual platforms is the design verification and analysis with the reference model of an executable functional specification. The glamor and headlines with be around the ‘new’ virtual platform solution, but–as with all good overnight success stories, the real followers saw this potential quite some time ago, and the answer to the puzzle above is the golden egg, which turns out in our story to be the golden reference processor model for tape-out quality testing. The one reference to unite all designers: System, Software, Hardware and DV can all use the processor reference model with confidence.

As a side note, Imperas celebrated both its 11th anniversary and record revenue in 2019. 2020 looks to be a great year and the team at Imperas are looking forward to working with all our partners and customers on verification and virtual platforms projects and solutions.

Tags: Predictions

This entry was posted on Monday, February 3rd, 2020 at 5:55 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.