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Yoan Dupret
Yoan Dupret
Yoan is the Managing Director and VP of Business Development at Menta – a leader in embedded FPGA IP cores for chips and smart sensors. Prior to his position at Menta, he held various managerial and technical positions at DelfMEMS, Samsung, CSR, Infineon and Altis Semiconductor. Yoan holds a PhD … More »

EDACafe Industry Predictions — Menta S.A.S.

 
January 7th, 2020 by Yoan Dupret

‘Moore’s Law Gives Way to More’s Law’

In 2020, we expect Kurzweil law of accelerating returns to apply and therefore 2019 trends to accelerate.

As the Economist magazine recently headlined, we are living through a chip and sensor renaissance. This is fueled by an unprecedented growth of devices of all shapes and sizes at the ‘Edge’, permeating both industrial and consumer markets. While the pundits lament the demise of ‘Moore’s Law’, there is a new law emerging which we should perhaps call ‘More’s Law’ – there will be more of these devices, emerging at an exponential rate.

While this is a great business opportunity for all of us in the hardware value-chain, it is also masking a hitherto unrecognized threat – the threat posed by the fracturing of the old computing order. For the first time in decades, we can no longer accurately predict the winning architectural or algorithmic solution for a given compute or communication problem – even for a two year event horizon.

This is happening because the rate of architectural and algorithmic innovation is outpacing traditional chip development cycles. Considering that it can take, on average, two years, and tens of millions of dollars to develop a new chip or a smart sensor, this is a major threat to the industry and a difficult challenge for designers.

How can we ensure that our shiny new device will not be still-born by the time it hits the market or will continue to be fit-for-purpose once delivered?

AI is a good case in point. There are around 100 companies around the world, all designing AI chips of one kind or another – mostly for edge devices, and all with radically different architectures. Not all will succeed.

While two years ago, AI training workloads were confined to hyperscale data-centers, we are now seeing a migration to the edge (because that’s where the data is), which was traditionally seen as an inference stronghold. The whole field is an alphabet soup (CNN, SNN, BNN, GAN, DNN) and just as we thought FP16 was essential, out come several start-ups saying INT8 is good enough with better latency and similar accuracy. Even Intel has had to make three different and incompatible acquisitions in this field in the past few years (Nervana, Movidius, Habana) as well as continuing to support FPGA based AI following its Altera acquisition.

The point is, no one really knows the winning answer (yet) and ‘disruptive and rapid change is now the new constant’ – probably for the next 10 years or so. This is not only true for AI, but also for communication protocols, encryption, compression, interconnect fabrics and cybersecurity. The old world order of computing has now fractured beyond recognition.

Sensors have not been spared either. While they are becoming ubiquitous in our lives, they now must also become ‘smart’ in addition to being more reliable, cheaper and easier to integrate. With these ‘smarts’ comes the need for reconfigurable algorithms – you can no longer rely on simple Kalman filtering and forget about it.

Separately, we are also observing a growing trend to customize merchant chips and smart sensors. Large customers (starting with hyper-scalers) are now demanding a degree of customization and are no longer satisfied with off-the-shelf offerings. The only way to achieve this is with some degree of reconfigurability in the design – otherwise development and inventory costs will spiral out of control.

With all these vectors for change, now is the time to design chips and smart sensors to be at least partially reconfigurable to adapt to emerging needs. We are seeing a clear trend towards highly heterogenous SoC architectures which clearly partition the design with these drivers in mind. The same also applies to power consumption which is of paramount importance for edge devices. Several companies now offer High Level Synthesis tools, including our partner Mentor Graphics, which help in that direction. In 2020, we expect new software offerings to enable better heterogenous partitioning of designs with reconfigurability in mind.

Coming back to ‘More’s Law’, this obviously not only means more chips but more changes in algorithms, architectures, and interconnects which only a low-power, field reconfigurable device can deliver. That’s why we continue to advance our low-power eFPGA cores which offer that reconfigurability and judging by the 50x increase in the number of enquiries we are receiving, it seems we are on the right track.

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