Helic: Blending the Long View with Pragmatic Realities

Taking guidance from their website, Silicon Valley based Helic provides “EDA software that mitigates the risk of electromagnetic crosstalk in high-speed and low-power SOC designs.”

The company’s products include VeloceRF, an inductive device compiler and modeling tool which provides DRC clean devices for geometries as low as 10 nanometers; RaptorX, a pre-LVS electromagnetic modeling tool; and Exalto, a post-LVS RLCk extraction tool that captures unknown crosstalk including electrical, magnetic, and substrate coupling.

In other words, Helic is a company with a very technical portfolio of products, which can be daunting if one wants to speak with the leadership.

But that was not the real problem posed during my recent conversation with Helic President and CEO Yorgos Koutsoyannopoulos. The last time the two of us spoke, he made a bet I could not pronounce his name correctly. I won that bet, although Koutsoyannopoulos then proceeded to pronounce my name correctly as well, something that fewer than 1-in-10 in EDA can actually do.

Alas during our recent conversation – the one documented below – the Helic CEO could still pronounce my last name correctly, but I stumbled over his.

In my defense, Koutsoyannopoulus has 16 letters, 56% of which are vowels, and I hadn’t practiced in advance of our call. My last name only has 8 letters, but 63% of them are vowels, so mine is actually more difficult to pronounce. I should not have let Yorgos best me in this contest. Next time I will be better prepared.

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WWJD: How are things going?

Yorgos Koutsoyannopoulos: Our business and focus are going very well. We are currently serving an emerging need, which is due to the migration of most SoC design to finFET and due to the fact that frequency and speeds have gone substantially higher.

We are serving the need to identify the source of crosstalk, and to remove the uncertainty related to that crosstalk. We analyze the layout of very complex SoCs and provide assurance that everything will go well after tapeout.

Between 2011 and 2014, we made big investments in the company to build a new engine. The data we used to help [in that effort] we collected from customers and foundries as they transitioned from 28 nanometers to the [smaller nodes].

Today, the majority of our engagements are at 16 nanometers, while the most interesting parts of the market are now at 10 and 7 nanometers. This is where most of the challenges are today, including the challenges related to finFET design.

We also have made a very big investment to build capability and capacity to deal with the size of the problem. That investment has paid off big time, so now we have huge SoCs being built by the large companies using our tools. We are providing a very proactive flow to those companies that [addresses] the root cause of crosstalk, and provides a cure for how to remove the uncertainty.

WWJD: Who is your competition, and how does your flow compare to the Big Three in EDA?

Yorgos Koutsoyannopoulos: There is a lot of competition in the analysis of the EM effects at the package and board level, the king there being Ansys.

But because of the size and complexity of the problems, and finFET technology, there is almost no solution today at the chip level. I say ‘almost’, because most people would use an EM solver [in that situation], but that is no longer enough.

WWJD: Do people know that their EM solver is not enough?

Yorgos Koutsoyannopoulos: Yes, of course.

I pick the example of Ansys, because they have installed a license just about everywhere. Their HFSS is everywhere [simulates high-frequency electromagnetic fields] and is used for boards and packages, and is a very powerful tool. But when designers cross the border in the SoC level, [they still] run into problems.

WWJD: Could there be a merger ahead between Helic and Ansys?

Yorgos Koutsoyannopoulos: [chuckling] That could be a scenario, but it’s not something we have even thought about.

WWJD: When and why was Helic founded?

Yorgos Koutsoyannopoulos: The company is 17 years old, we were founded in 2000.

We started in Athens, where we had a team that had a combination of backgrounds between software development, electromagnetics, and analog and RF design. That combination helped us to shape a solution that was meaningful for RFICs, even back then.

Then we realized this was a problem that all SoCs faced, and we transitioned to solutions for CPUs, GPUs, FPGAs, server chips, memories and memory I/Os. Our technology covers a very broad range of applications, anywhere there might be a cross-talk situation. This is where we are very useful.

WWJD: Has the company had any announcements recently?

Yorgos Koutsoyannopoulos: We did have a very interesting presentation with TSMC at their partners forum that demonstrated extremely well our flow and the methodology, but no announcements related to customers, unfortunately. We are not allowed to name them, so there is nothing to share in that area.

[chuckling] Of course, I wish I could share more names with you, although based on the applications that we are discussion, it might be [possible to figure it out]. We are very active in most SoC designs that are at 16 nanometers and below.

WWJD: Is it a big problem when customers won’t allow you to release their names, or just something you live with?

Yorgos Koutsoyannopoulos: This is not a problem specific to EDA, enterprise software is the same. Always when there’s a limited list of suppliers, customers want to hide their relationships with those suppliers. It is a problem, a big problem.

I really do wish I could share this information, the case studies with our customers, and why our technology is important for our customers.

WWJD: How are we doing with Moore’s Law?

Yorgos Koutsoyannopoulos: I do believe we are converging gradually on a limit, but I do not believe 5 nanometers is the limit. There will be one or two more nodes on the way, as we understand CMOS today.

I also believe there will be an evolution of the finFET – let’s say, a minor disruption in the way we understand CMOS – that will take us until at least 2025. What technology will prevail after that, I truly don’t know.

I pay close attention to the other candidates that may extend the life of CMOS, but I really don’t know what will be successful commercially. As we understand CMOS today, we expect a lifespan of at least 10 years.

WWJD: Will there be a new breath of life for the older nodes, given IoT is working there?

Yorgos Koutsoyannopoulos: Yes, I agree. A part of the IoT application space will probably use older nodes.

Because we are targeting ultra-low power and ultra-low complexity types of applications, we don’t really need 7 nanometers for IoT devices. We need ultra-low cost, a fraction of a dollar or just cents. That’s one category of IoT that will work at the older nodes.

But there’s another category: Really high-end sensors, which are being developed at the more high-end, smaller nodes. The thing there that’s really hard to put our arms around, however, is the volume.

It’s hard to conceive of the amount of chips that will be shipped to serve this new market. And I don’t think we should treat IoT as a unified market. Instead, we will gradually understand the different market segments from an applications point of view.

Given the chips we support and help develop, there are some applications that have already emerged, and we understand. But in the long run, it’s hard to understand what the depth and breadth of applications will emerge.

Nonetheless in the end, applications, new companies, and new technologies will emerge from all of this – while security will be the biggest challenge. The mid-level of software that will be needed to handle the massive amounts of data that will emerge from all these devices is the biggest challenge I see. Again, I think the long-term is not clear.

And I want to be a pragmatist. Yes, I understand the ideas, but how can we make money out of it? If we try to forecast revenue, we can’t be that specific for the next 12-to-24 months. So there are also new business models that must emerge, and that’s never easy.

From an EDA perspective, however, these are new design starts – a massive wave of new starts, either in the older nodes or for high-end designs – which is all good news for us.

Also, we are asking: Is there another opportunity for EDA to move higher, to be [seen] as enterprise software? To move higher in the hierarchy, to provide more value beyond design?

We are looking at all of that, the development of technologies for many different applications. We are exploring all of this at Helic.

WWJD: This sounds like a strategy that requires taking the long view.

Yorgos Koutsoyannopoulos: We are solving problems today with designs with multi-billions of transistors, but we are also working in higher layers of the stack. We believe we need to look at all of these levels.

WWJD: How do you find bright young engineers, your next generation of employees?

Yorgos Koutsoyannopoulos: As you know, the market for employees has becomes extremely competitive. It’s very hard to attract talent, and we face a [particular] challenge in EDA.

The younger engineers tend to want to go to the ecosystem companies like Facebook and Twitter. It’s hard to attract talent to EDA. It’s not as sexy as it was 10 years ago.

Nonetheless, at Helic we are very selective. We try to reach out to a very specific [population], giving them information and using all sources we can get.

We try to attract engineers from semiconductor and design companies, or other software companies not related to EDA, because we have very specific needs in software development. And we reach out to different areas in the US, not just Silicon Valley.

Helic has a research team in Athens, we have a lot of talent in Greece. We try to attract young engineers in Greece, and we recently opened an office in Ireland. There’s also a lot of software talent there as well.

WWJD: Why belong to the ESD Alliance?

Yorgos Koutsoyannopoulos: The ESD Alliance brings a wealth of services, information, and networking to the industry.

First, it’s really important to be able to share experiences between fellow companies in the ecosystem. It’s very important to exchange information on business models, and the challenges related to business models and sales, because we are in the same food chain.

We also get a lot of support from the executive team of the ESD Alliance on legal issues. Examples include export control issues, federal taxation, and accounting principles. These are subjects that matter to the whole ecosystem. The ESD Alliance helps a lot in organizing and sharing this information efficiently. This is something of great value, of huge value to us.

Of course, the networking part of the ESD Alliance is very important, and helps to build bonds and
design flows that we all serve. We all know that we co-exist in the design flows of all of our customers, so it’s important to network within our ecosystem proactively.

WWJD: Is there something you would like to see the ESD Alliance work on that’s not currently being addressed?

Yorgos Koutsoyannopoulos: The thing I recently proposed to Bob Smith [ESD Alliance Executive Director] was to align with DAC, or certain ones of the ESD Alliance customer events, to move closer to where the design communities get together.

DAC, for example, has become kind of distant from the tool user base. Somewhere we need to better align our events, our gatherings, with the communities of our users.

WWJD: How do you do that?

Yorgos Koutsoyannopoulos: The simplest way would be to have an event close to a trade show or a conference that is mostly related to design.

For instance, ISSCC is a big event in San Francisco every February, which is mostly design companies and design teams showing off their chips. That’s just one example of an event where design groups get together and talk about their designs.

We should be at ISSCC to listen and participate as an alliance. Currently, unfortunately, we are kind of out of that circle of discussion.

WWJD: What are some of the broad topics the ESD Alliance might work on over the next couple years?

Yorgos Koutsoyannopoulos: One of the biggest challenges of the industry, and one the ESD Alliance can deal with, is the actual business model that the industry is following.

Today there is little connection between the actual prices of the products and the value they provide. In the long run, sales negotiations have deviated completely from that central topic: What is the price, and how is that defined relative to the value of the software?

WWJD: In other words, EDA vendors have no skin in the game? They want to paid whether the design is successful or not?

Yorgos Koutsoyannopoulos: That is one extreme, the far extreme, because practically – even if you want to share in the revenue – it is a hard thing [to organize].

Instead, we have gone to the other extreme. We have arbitrary pricing that traces nothing from what it actually offers.

I hate both extremes. I don’t want to share the revenues of customers, but I also hate the other extreme. Whenever I negotiate the prices, it’s the worst discussion with customers. They say there is no relationship between price and value. And all of the legacy that the big companies bring [to the situation] – the all-you-can-eat deals – these are not helping.

I would like the ESD Alliance to facilitate a dialog about all of this, to bring together the key stakeholders. Yes, it’s hard to change things, but I’m trying because I think it can be done.

There is good news here. The big semiconductor companies are using models with their suppliers that would provide a return on their investment. They are trying to maximize the use of the tool assets [they purchase] and trying to be more open to discussion. They’re not totally against the idea, they understand this would maximize their investments in the tools.

Yes, the business model is the grand challenge the ESD Alliance could address.

WWJD: What is the funniest thing that’s ever happened to you in your career.

Yorgos Koutsoyannopoulos: We are pretty serious in this company and we are not alone in that, although there are small things that are amusing here and there. For instance, in my company it is a good thing that my old code doesn’t exist anymore. The last line was removed in 2008.

WWJD: Is Helic now permanently located in Silicon Valley?

Yorgos Koutsoyannopoulos: Yes, for a few years now.

In 2009, I moved to San Francisco, and later came down to the south part of the Bay Area. I really enjoy this place, it’s very similar to Greece.

The weather, the diversity of people, and the quality of life are all amazing.

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Tags: Ansys, Bob Smith, electromagnetic crosstalk, ESD Alliance, finFET, Helic, TSMC, Yorgos Koutsoyannopoulus

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