Innovation: does Voltus prove CDNS still has what it takes?

Cadence is announcing this week a new product for power integrity and signoff called Voltus, which the company says solves several problems simultaneously.

Per a phone call with Cadence Director KT Moore, one of the challenges in power signoff is that it takes a lot of time: “When designers look at analyzing power for the block, chip or package, current analysis techniques can literally take days, so designers are looking for a faster solution. What Cadence believes to be true about Voltus is that this product is 10x faster than any existing solutions available today. Because of that, we know the customers are very excited.”

“The other issue with power signoff,” Moore said, “is that it needs to be accurate. You can make a product a thousand times faster, but it’s of little value if it’s not accurate. With Voltus, however, we’re maintaining the same accuracy compared, for instance, to Spice or whatever the customer’s expectation reference is. But there’s an additional level of accuracy in Voltus that’s also important.

“Remember when Cadence introduced the Tempus timing signoff tool back in May? Now when you do static timing, you can see how the design will look at multiple corners and temperatures. But one thing’s been missing and that’s what happening with your IR drop: If you have voltage drop on your VDD or ground rail, if you change the functionality it won’t work properly.

“So we’re integrating both Tempus and Voltus to work together. Now anybody who’s looking at the effect of IR drop on static timing can also look at the related power issues. The tools run side by side.”

“Between last May when you introduced Tempus and today,” I asked, “what have people been doing to solve these issues?”

Moore said, “Previously, it was much more of a manual process where you had to make approximations and judgment calls: Which timing windows were the right ones to look at for power? With Talus, you have much better visibility and accuracy as to where your high events are in timing, and now with Voltus you can apply voltage drops in those areas.”

“Are there portions of the process that are still manual?” I asked.

Moore said, “Yes, in that you still need to identify areas of high activity, but that’s the extent of it.  Designers generally know for certain operations in a design, those areas are going to be more power intensive, so it’s still somewhat intuitive. But once they identify those windows, they can do the calculations and determine the impact of static timing.”

“In addition to being integrated to timing,” he added, “we’ve also integrated Voltus into other aspects of our design environment, including Encounter and Virtuoso.

“Physical implementation optimization can be done at different levels. But in the digital space, for example, if a customer’s laying out a chip in Encounter and developing a power grid structure to look at course placement, they can run Voltus to get a rough idea to see if they can get the power supply needed to multiple blocks. They can also get feedback from Voltus through an ECS file that will help guide changes for either Encounter or other digital implementations.”

“In addition, as you know,” Moore said, “we acquired Sigrity last year for board analysis, so we’ve integrated Voltus with those tools as well. Passing the models back and forth, we’re generating very accurate models for the board design environment.

“We’ve also integrated Voltus with Palladium for co-simulation. We can take vectors from Palladium and drive Voltus as well.”

Moore posed a rhetorical question: “So what do we think is truly revolutionary here? Well, when we talk to customers about their signoff environment, they admit there hasn’t been a lot of new technology in the area of static power and timing. Not a lot of innovation.

“At Cadence, however, we’ve wanted to inject new technologies, especially in performance. With Voltus, we’re doing that by taking advantage of massively parallel execution.

“Back in 2004 or 2005, the average computer was dual core, perhaps a Linux box with 2 cores. Now today, even low-end systems are quad core, with the average being more like 8 cores on the mother board. We want to be able to scale with that. But as compute power goes up, the software should be able to take advantage of that scaling without being rewritten, so we’re architecting our tools to take advantage of that capability.

“Voltus will scale, with better performance, across a network of multiple CPU machines. The only limiting factor we’re seeing is the size of the design. Running a small design across a large number of CPUs produces only diminishing returns, but if you take a large design, you can definitely see scalability across a larger number of CPUs or machines.

“Voltus has been designed for performance on massively parallel systems, whether looking at a flat netlist or a hierarchical netlist. In both cases, the performance will be better. And we’ve worked with some of the leading foundries to be sure we’re accurate per all of their requirements.”

“But even with all of this,” Moore emphasized, “the key thing about Voltus is that it’s 10x faster while maintaining fully accurate power and sign off integrity. This is the very first time designers have access to tools working together for both static timing and power analysis.

“Along with offering faster, more accurate technology, Voltus is giving designers the opportunity to look at sign-off problems earlier in the design phase. This is innovation.”

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Press Release Endorsement …

* IDT Senior Director of the Design Automation Group Alan Coady: “IDT produces industry-leading products across a wide range of nodes and applications, and we were pleased to see the Voltus technology delivers up to a 10X performance improvement across various test cases ranging from 180nm to 28nm designs. With the accuracy, ease of use, stability and support we received, we are considering widespread deployment of this new technology from Cadence.”

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Tags: Cadence, Encounter, IDT, KT Moore, Palladium, power signoff, Sigrity, Tempus, Virtuoso, Voltus

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