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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

DAC 2013: EDA news in anticipation of Austin

May 30th, 2013 by Peggy Aycinena

** Aldec announced the launch of Spec-TRACER, which helps organizations manage, control and track requirements throughout the entire FPGA/ASIC development lifecycle by streamlining and automating the requirements engineering process such as capture, traceability, requirements versions tracking, results management and reporting. The new product is targeted for use in safety-critical industries in which rigorous certification standards exist, such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear.

Louie De Luna, Aldec DO-254 Program Manager, is quoted in the Press Release: “Ensuring that traceability exists throughout the entire development lifecycle is crucial to proving that the product has been designed and tested through a requirements-based process, from top-level design requirements to HDL source code, and from verification test cases to the testbench and through to the simulation results. Spec-TRACER is exactly what the avionics industry needs to help satisfy the traceability objectives of DO-254.”

Cadence Design Systems announced Tempus Timing Signoff, a new static timing analysis and closure tool designed to enable SoC developers to speed timing closure and move chip designs to fabrication quickly. The company says Tempus Timing Signoff represents a new approach to timing signoff tools that allows users to shrink timing signoff closure and analysis for faster tapeout while producing designs with less pessimism, area and power consumption.

New features introduced in Tempus Timing Signoff Solution include: The first massively distributed parallel timing engine which can scale up to hundreds of CPUs; Parallel architecture which allows Tempus Timing Signoff Solution to analyze designs in the hundreds of millions of instances without compromising accuracy; A new path-based analysis engine that leverages multi-core processing to reduce pessimism; Multi-mode, multi-corner (MMMC) analysis and physically-aware timing closure that leverages multi-threaded and distributed timing analysis.

Lip-Bu Tan, President & CEO at Cadence, is quoted: “Achieving design closure on today’s complex SoCs is a significant challenge to hitting market windows. We developed the Tempus Timing Signoff Solution in collaboration with customers and ecosystem partners to address this challenge.”

Concept Engineering announced a new SPEF (standard parasitic exchange format) interface to the company’s debugging tools, SpiceVision PRO and StarVision PRO. The SPEF file format is an IEEE standard to define parasitic networks; it contains precise information about interconnections and the related parasitic components.

The company says the new SPEF interface, and the already-available DSPF (Detailed Standard Parasitic Format) interface, give design engineers using SpiceVision PRO and StarVision PRO an easy way to analyze and explore parasitic structures in order to better understand, manage and optimize timing, signal integrity or IR-drop within their designs.

Gerhard Angst, CEO & President of Concept Engineering, is quoted in the Press Release: “Now, with two dedicated interfaces available, customers will be able to more easily understand and manage extracted parasitic netlists and the impact of parasitic elements on their designs. The SPEF and DSPF interfaces provide users with a comfortable way to visualize and analyze the most important post-layout data formats of today’s advanced design flows.”

Forte Design Systems announced that LG Electronics has adopted Cynthesizer SystemC HLS for its next-generation DTV design project. Per the Press Release, “Cynthesizer is the first high-level design solution that closes the gap between electronic system level (ESL) design and register transfer level (RTL)-to-GDSII flows.”

Jin-Gyeong Kim, Research Fellow, DTV SoC Development Department, SIC Lab at LG Electronics, is quoted: “While our department only recently began deploying Forte’s Cynthesizer, we’re seeing immediate productivity improvements and reduced development time. We’re confident we selected the right vendor for our needs.”

G-Analog Design Automation, a new privately funded EDA startup headquartered in Hsin Chu, Taiwan, announced it is formally launching its operations and will focus on the development and delivery of its next-generation simulation and characterization software, GChar, for custom ICs.

Per the Press Release: “With smaller geometry in advanced processes, process variation becomes an important issue for 28nm and below designs. Monte Carlo simulation or OCV analysis is needed. Running Monte Carlo simulations and obtaining OCV tables are even more computation intensive than cell characterization. Generating process variation data for a design has become a major issue for today’s design community.

“G-Analog Design Automation offers tools to address circuit verification and characterization needs for nanometer custom digital, memory and mixed signal circuits. G-Analog has developed a next-generation simulation and characterization solution. With innovative proprietary GPU based simulation technology, the GChar product delivers breakthrough performance and SPICE accuracy.”

The Press Release also says, “G-Analog has experts in the area of circuit simulation and design of ICs, with over 20 years of experience at leading companies including GlobalFoundries, Chartered, Nassda, Synopsys, and EPIC serving as the basis for a next-generation solution for circuit analysis and characterization.”

Dr. Jeff Tuan will serve as President and CEO of the company. Prior to G-Analog, Tuan was Deputy Director at Chartered Semiconductor and GlobalFoundries where he managed IP and test chip development. In addition, he was one of the co-founders of Nassda where he served as VP of product development of the HSIM product. Before Nassda, Tuan served as R&D director at EPIC and Synopsys, where he oversaw product developments of the RailMill, TimeMill and PowerMill products.

Imperas Software Ltd. announced the release of its 2nd generation virtual platform development and multicore software design kit product offerings. The company says the new Developer range and Multicore Software Development Kit products utilize a simulator that leverages a Just-In-Time code morphing mechanism:

“Imperas’ ToolMorphing technology extends this mechanism to generate tool and model code together, which allows Imperas’ customers to build models of their electronic hardware platforms and to integrate existing, industrially proven processor models that include tool and simulation capabilities, adding advanced, unique software development features operating at a high performance level.”

Each of the Developer products include: iGen model generator, used in the creation of the platform model and the behavioral components that populate the platform; Imperas Model library of 100+ CPU model variants that includes ARM, Imagination MIPS, Power, Synopsys ARC, Cadence Tensilica, Renesas, and others; The Imperas simulator, which executes the platform, peripheral, and CPU models, and allows compiled binaries of bare metal embedded software, embedded operating systems and applications to execute un-modified on virtual platforms, in turn running on desktop PCs.

The Multicore Software Design Kit, M*SDK, product includes all the capabilities of the Developer product, and layers on top a powerful suite of verification, analysis and profiling (VAP™) capabilities, as well as 3Debug™ an advanced multicore debugger that operates across the spatial, temporal and abstraction domains.

Simon Davidmann, Founder and CEO at Imperas, is quoted: “The embedded software industry has just started to realize the potential of virtual platforms, and the Imperas approach layers verification knowledge, performance simulation expertise and customer insights to revolutionize the embedded software development process. This new technology is already dramatically reducing our customers’ engineering schedules while increasing their product quality.”

Premal Buch, VP of Software at Altera, is also quoted: “Given the wide variety of customer applications for our SoC FPGAs, our software stacks require rigorous and comprehensive testing. Imperas’ M*SDK has proven to be an outstanding environment for the validation and analysis of operating systems, drivers and firmware. Verification using the Imperas solution not only accelerates software bug discovery, but also provides a rapid understanding of the root cause of problems.”

Martin Baker, Senior Manager, Ecosystem and Business Management for the Automotive Business Unit of Renesas Electronics America, is also quoted: “Imperas is launching some very interesting approaches to processor modeling and software testing. Historically processor models have been used in relatively small numbers, despite their enormous benefits,” said “The Imperas business model has the potential to make processor modeling an affordable approach used widely across the industry.”

Mentor Graphics has teamed with OpSIS and Lumerical Solutions to develop “a complete EDA-style, full flow PDK for the OpSIS IME (Institute of Microelectronics) silicon photonics process.

“The OpSIS PDK relies on technology from Lumerical Solutions for optical simulation that is set up to let users create and manage Lumerical INTERCONNECT projects inside the Pyxis environment. Lumerical INTERCONNECT is used to provide system level optical analysis of integrated silicon photonics circuits. Compact model development work is ongoing using Lumerical’s FDTD Solutions, MODE Solutions and DEVICE to complement the experimental data.”

Michael Hochberg, Co-founder & Director at OpSIS, is quoted in the Press Release: “We are extremely pleased with the industry collaboration and support OpSIS had received in developing a PDK for use by silicon photonics designers. By working together, we are making silicon photonics a reality for multiple applications, research efforts, and companies that would not be able to do such work independently.”

James Pond, CTO at Lumerical, is also quoted: “The simulation of photonic circuits inside an EDA-style flow is extremely challenging so we are excited to reach the critical step of exporting a circuit to INTERCONNECT for simulation. We look forward to collaborating with our partners and also the end users to ensure that this design and simulation flow meets their needs in the future.”

Linda Fosler, Director of Marketing, Deep Submicron Division at Mentor, is also quoted: “Silicon photonics is becoming an important design enabler, especially for data communications. As this technology finds its way into more and more chips, it is extremely important that traditional EDA providers partner with the companies providing dedicated photonics tools and with foundries supporting silicon photonics. We are very pleased to be part of this collaboration.”

OneSpin Solutions announced Jim Cantele has been appointed Vice President of Worldwide Sales, reporting to President & CEO Raik Brinkmann.

Prior to joining OneSpin, Cantele served as VP of Global Sales and Field Operations for Polyteda Software. He has also worked at a number of EDA and semiconductor companies in a variety of technical management and management positions, including Cadence, Celestry, Mentor Graphics, Oridus, Samsung and Supertex.  Cantele has a BSEE from California State University, Sacramento, and an MS in Math and CS from San Jose State University.

Real Intent announced a combined RTL sign-off flow for both CDC and DFT resulting from a collaboration with DeFacTo that integrates DeFacTo’s SIGNOFF solution with Real Intent’s Meridian CDC.

Chouki Aktouf, President & CEO at DeFacTo, is quoted in the Press Release: “Our collaboration with Real Intent is a natural outcome of our complementary product offerings that help eliminate complex failure modes of SoCs at the RTL stage of design.”

Hamad Emami, VP of Worldwide Sales at Real Intent, is also quoted: “DeFacTo offers unique technology for testability sign-off at the pre-synthesis stage of design. By partnering with DeFacTo, we bring design teams the best platforms in the market for RTL sign-off for both DFT and CDC issues.”

Silicon Frontline Technology announced two semiconductor analysis products, ESRA and Ethan. ESRA is targeted at designers needing to verify the full chip for ESD reliability, pinpoint areas susceptible to failure, work on pre- and post- LVS clean designs, handle CDM (charged device model), MM (machine model) and HBM (human body model) ESD events, and optimize ESD device area. Ethan offers electro-thermal simulation of power devices with static and transient analysis. It automatically calculates the thermal impact on electrical performance while highlighting thermal gradients, thermal sensor operation, and impacts on sensitive analog circuits.

Yuri Feinberg, CEO at SFT, is quoted: “ESRA is the first product to offer comprehensive ESD verification, covering full chip and cell level. Ethan provides electro-thermal analysis for power devices, taking into account the semiconductor and package.”

Synopsys announced a collaboration with ACE Associated Compiler Experts that the companies say “extends their multi-year collaboration to integrate ACE’s optimized compiler technology with Synopsys’ Processor Designer product line.

“The system Synopsys is licensing is ACE’s complete CoSy advanced compiler development system. CoSy represents hundreds of years of combined compiler expertise, spanning a wide range of processor architectures including RISC, DSP, and VLIW. ACE’s dedicated compiler experts will be working alongside Synopsys’ application experts in projects that require the joint optimization of embedded processor architectures and the associated compiler.”

Martijn de Lange, Founder and CEO of ACE, is quoted in the Press Release: “When companies adopt CoSy, they gain access to a production-quality system to build optimized compilers for the most extreme processors.” The integration of CoSy/CoSy Express with Synopsys Processor Designer gives developers of application-specific processors a quick path to an optimized compiler.”

Johannes Stahl, Synopsys’ Director of Product Marketing for system-level solutions at Synopsys, is also quoted: “Working closely together, Synopsys and ACE can help product development teams take maximum advantage of the Processor Designer tool set and ACE’s proven compiler technology to accelerate increasingly software-dependent product development cycles.”

Synopsys also announced availability of the Virtualizer Development Kit (VDK) for Renesas RH850 MCUs to accelerate software development, system integration and test for RH850-based automotive applications such as body, power-train/hybrid and chassis/safety control. The new VDK is the first commercial deliverable from the Center of Excellence collaboration between Renesas and Synopsys. and enables automotive engineers designing RH850-based ECUs to start developing, integrating and testing software months before ECU hardware is available, resulting in higher product quality and reduced development cost.

Akihiko Watanabe, Department Manager of Automotive Electronics Core Technology Department, Automotive Solutions Business Division, 1st Solution Business Unit at Renesas Electronics Corporation, is quoted: “The availability of the Synopsys VDK for Renesas’ RH850 MCU marks a key milestone in our long-term collaboration and provides developers of RH850-based applications a productive software development solution. As software content and complexity in automotive ECUs continues to grow, our customers can take advantage of leading virtual prototyping technology that has been adapted for the RH850 family, so they can start their software development tasks earlier and accelerate system integration, test and validation.”


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