DVCon 2013: in 25 words per sound bite [or less]

I don’t know about you, but I thought DVCon 2013 in San Jose this week was super. There was a lot of energy, I never heard anybody say the tools are broken (something industry pundits have been droning on about for years), attendance at the conference set a new record, both verification and design guys seemed to indicate that verification is still important enough to remain discrete from design, and SystemVerilog is fulfilling its promise.

The following list of 15 sound bites is not a complete representation of all that was said or debated at DVCon. Nonetheless, it’s an interesting list and reflects some of the information and opinions showcased during the week.

15 – Systematic verification methodologies are moving from the unit level, to the connectivity level, to the level of IP integration and data path, to the system level. [Wally Rhines]

14 – When it comes to language usage, VHDL is dropping off, as is Verilog, Vera, and e. SystemC has leveled off, C/C++ has shown some increase, but SystemVerliog is hugely growing in usage. The bigger the design, the more likely SystemVerilog is being used. [Wally Rhines]

13 – SoC design today involves many different specialists. Along with the verification guys, it also includes logic designers, RTL guys, embedded software guys to develop drivers, software developers, OS validation guys, test engineers, architects, place & route specialists. And all of this requires a lot of communication. [Ziv Binyamini]

12 – Hardware designers don’t want to learn to program FPGAs. That’s for software types. Design engineers don’t want to do verification. They want to do design. Verification engineers don’t want to go away. They want to be employed doing what they do best, verification. [Anon]

11 – With engineering teams there is always a tendency to resist new techniques. [John Goodenough]

10 – Specification documents have to be maintained, and they need to be actionable and optimal. You have to understand who the customer of the spec is, and that always includes the Verification Team, among others. [Harry Foster]

9 – There are significant cultural changes underway. I know of at least one company where there’s now a VP of Verification & Validation, elevating verification engineers from their previous status as second-class citizens in the industry. [Harry Foster]

8 – Verification is best when done with extensive pre-planning, and that plan is best when all stakeholders are required to have a say in devising the document. No plan should be set in stone. It should be a living document that’s consulted regularly and respected, yet is also open to revision when thoughtful consideration warrants such changes. [Cadence-sponsored Best Practices Panel]

7 – Each company sees a diversification of problems across the widely differing topologies of chips being designed today, and it’s more than just company to company. Today, it’s chip to chip within the same company. [Brian Bailey]

6 – Power dissipation has been keeping our designs at about 30 percent of the available silicon, but now that we’re getting a handle on the power problem, we are enabling designers to use more and more of the available silicon. In the next year, designs will blossom from a little over 100 million gates to 400 million gates and beyond, which will exacerbate the verification problem. [Gary Smith]

5 – Multiplatform-based designs are what’s happening in IP. The IP of today are the platforms in themselves, which is why a new group is popping up called the Assembly Team. They’re taking the platform being designed by the different groups and assembling them into a final system, which also exacerbates the verification problem. [Gary Smith]

4 – General-purpose chips are becoming a thing of the past. We will get to 1 million distinct design starts by enabling tools and methodologies to customize everything up and down the stack. [Anon ASIC guy]

3 – General-purpose chips are the thing of the future. Everything will be differentiated in the software residing on an inexpensive reconfigurable hardware fabric. [Anon FPGA guy]

2 – There are a wide range of abstraction choices for software models, but at the hardware level you’re limited to clock cycles. [Dave Rich]

1 –  The industry feels dynamic and full of optimism for the future. [WWJD]

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Tags: Brain Bailey, Dave Rich, DVCon 2013, Gary Smith, Harry Foster, John Goodenough, Wally Rhines, Ziv Binyamini]

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