May 31st, 2012
Stop the presses! Someone other than the CEO of Mentor, Synopsys, or Cadence is going to be the Chair of EDAC.
What? Has the world come to an end?
Nope, but it turns out that even staid EDAC has, at last, learned how to innovate. It turns out that Mentor, Synopsys, and Cadence have, at least, seen the light and decided that they shouldn’t always be at the head of the class. As of yesterday, May 31st, there’s a new Chair at EDAC and it’s Kathryn Kranen, President & CEO at Jasper Design Automation.
Kathryn, of course, is well known within the EDA community. She’s been CEO at Jasper since 2003. Prior to Jasper, Kathryn was CEO of Verisity Design, and earlier on served as VP of North American sales at Quickturn. At the outset of her career, after earning a BSEE at Texas A&M, she worked as a design engineer at Rockwell, and then joined Daisy Systems in advance of her role at Quickturn.
In addition, Kathryn was named the 2005 recipient of the Marie R. Pistilli Woman in EDA Achievement Award, and has been an extremely hard working member of the Board of Directors of EDAC for many years.
I am personally elated at the news, and wish Kathryn all the best!
If Silicon Valley is all about articulating and executing on a vision, then Santa Clara based Uniquify is all about Silicon Valley. The company has been in business since 2005, and since that time has worked to crystallize and clarify its vision and road map.
The vision is succinct and to the point: Make creating chips easier and faster, and with better results.
And from what I heard on a lengthy phone call today with Uniquify CEO Josh Lee, the company thinks they’ve nailed it, realizing that vision in three distinct ways. Per Lee, “Number one is design services. With us this is a different beast than in the usual sense in that we start from a spec or idea from our customer, and take it all the way to GDS.
“In the past, design services – which emerged in the mid-1990s when the industry moved from the ASIC to the COT model – were either dealing with logical design or phsycial design. At Uniquify, however, we are doing them both together. As a result, our core business is best described as ‘from spec to GDS’.
Calypto Design Systems, Inc. announced Catapult Low-Power (LP). For those that were wondering why Mentor had given Catapult-C to Calypto, and those who having accepted the transfer were wondering what in the world Calypto would do with it, the answer arrived today in the form of a product announcement.
To begin with it is clear how Catapult-C fits with the original Calypto products. I t is a link between ESL and RTL that is parallel to the SLEC product. But the new release is much more than that. It incorporates some of the SLEC technology as well as some of the PowerPro technology, providing a HLS that is also power aware.
I recently talked with Atrenta’s senior director of product marketing, Kiran Vittal, about power management/optimization trends and approaches that we’ll see at DAC next week.
Ed: So power, or rather more rigorous power management will be a hot topic at DAC. How come? What will be different this year?
Kiran: As we all know, power is of the biggest concern to both mobile applications as well as wired devices. An average mobile SoC is over 100M gates operating at over 500Mhz and designers do everything necessary to apply all known power management techniques to reduce power.
It will also be interesting to see that application processors for cloud-based servers are now being designed with over 10 power domains to shut off power in non operating regions and a quad core SoC consumes around 5 watts during maximum utilization and as little as 0.5 watts during idle time.
Ed: So what approaches are we going to hear about @ DAC?
Kiran: We are going to hear about power management, power intent creation using standards, power optimization, power verification and sign off.
Ed: How do they stack up?
Kiran: It is very clear that any power management and optimization technique applied at the gate level is too late to make any difference to the aggressive low power requirements. Early power planning, RTL power estimation, automated reduction around both registers and memories and early power intent verification is the only way to achieve today’s aggressive power goals for both mobile as well as wired chips.
Stop by Atrenta’s booth (#2230) to talk about Kiran’s views with him!
Note: Lee PR does work for Atrenta
The IEEE CEDA would like to remind the EDA community to help recognize outstanding achievements in the field through the Phil Kaufman award. The nomination deadline is coming up: Saturday, June 30, 2012!
The yearly Phil Kaufman Award for Distinguished Contributions EDA is sponsored by the EDA Consortium (EDAC) and the IEEE Council on EDA. The award honors an individual who has had a major impact on the field of EDA in business, industry direction, promotion, technology and engineering or educational or mentoring. Impartiality is provided to all nominees, without regard to race, gender, age or national origin.
EVE: a question of Focus
May 30, 2012 by Peggy Aycinena
Founded in 2000 in France, EVE has been a highly visible part of the EDA landscape for over a decade. In the week prior to the Design Automation Conference in San Francisco, I spoke by phone with Lauro Rizatti, General Manager and Marketing VP for EVA-USA, headquartered in Silicon Valley.
Lauro said that EVE is not releasing specific news at DAC because the company is launching the newest version of its ZeBu emulator in November 2012, the ZeBu-Server2 based on the Xilinx Virtex 6. Following that, EVE will be releasing the ZeBu-Server3 in mid-2014 based on the newest version of Xilinx Virtex 7. It’s not a coincidence that EVE’s hardware, built around ‘off the shelf’ FPGAs, enjoys a new release every two years.
Per Lauro: “Working with FPGAs, we don’t have to wait for internal, custom chip development to move forward. And because we use Xilinx, we ride their technology road map. Every 2 years they launch a new platform, and every 2 years so does Eve. We think we have a brilliant strategy, and the results can be seen in our earnings. We recognized $52 million revenue and $62 million in bookings over the last 12 months.”
Both Synopsys and Mentor reported their Operating Results within one week of each other. For Synopsys it was its second quarter results, while Mentor reported its first quarter results. Both companies had good quarters, although Synopsys, as it is to be expected, had better overall and relative results than Mentor.
Synopsys Is All Good News
There got to be an end: it is just not human! But I do not see any changes to Synopsys good news, quarter after quarter. It may be in the genes, it may be in the coffee, or it just may be in old fashioned good work. But first an outing then the numbers.
I have had a relationship with Synopsys since 1990, never as an employee, but as an early user of Design Compiler, then as somewhat of a competitor, and finally as a professional observer. During all that time I have known Chi-Foon Chan who joined Synopsys in 1990 and until May 23rd was the President and COO of the company. I know relatively few people that knew that Chi-Foon even existed. He worked in the background, but worked very effectively. By comparison everyone knows who Greg Hinckley is at Mentor. I suppose that when one is in the same organization as Aart de Geus, it is not very difficult to stay in the background. But it takes a lot of stamina to do so and outperform expectations for a long time. Most people seek the lime lights, or at least their piece of sunshine. So Chi-Foon is out of the closet, and everyone now knows what I have experienced. Talk EDA with Aart or Chi-Foon and the result is the same.
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