March 29th, 2012
3D in Monterey Next Week
March 29, 2012 by Ed Lee
This event is happening next week! Worth signing up if you can get down
EDPS is coming up again! It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.
This year, the 3D topic will be the focus of day two.
First and foremost, Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two. (see his views on 3D standards: https://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/
Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:
* Stephen Pateras of Mentor on BIST for 3D ICs
* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors
* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks
Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence, with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.
* Herb Reiter
* Samta Bansal of Cadence
* Dusan Petranovic of Mentor
* Deepak Sekar of Monolithic 3D
* Steve Smith of Synopsys
* Phil Marcoux of PPM Associates
Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.
John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during “3D Day”, Friday, April 6.
Very worthwhile to attend if you can get the time off.
Monterey: Top Ten @ EDPS
March 29, 2012 by Peggy Aycinena
Here are the Top Ten reasons to be going to EDPS next week in Monterey:
10) Next week’s a lighter work week for most and the Monterey Peninsula is beautiful at any time of the year, but particularly in the spring.
9) The Electronic Design Process Symposium is in its 19th year, and everybody who’s anybody in EDA and its adjacencies has attended at one point or another.
Eight) The topics discussed at EDPS have always tracked the trajectory of the industry. In 2000, those topics included: deep sub-micron, distributed and web-based design methodologies, designer productivity, and maintaining modularity in an integrated design flow.
Here in 2012, technology evolution has driven a completely different set of topics: embedded processors, FPGAs, ESL, NUMA, EDA in the Cloud, Big Data and the Big Servers that serve them, low-power design, and 3d-ICs, among others.
7) Going to conferences is as much about conversations outside the sessions, as it is about presenting or listening within the sessions. EDPS is a boutique conference, where I promise you’ll have a chance for substantive conversations with the speakers, both inside and outside of the sessions.
ISQED 2012 Photo Gallery
March 28, 2012 by Graham Bell
I had the pleasure of attending the International Symposium on Quality in Electronic Design (ISQED) 2012 held in Santa Clara, March 19-21 at the Techmart. I took some photos at the event. See if you can spot Georgia Marsalek of ValleyPR in any of the pictures.
The folks who run Design West, happening this week at the San Jose Convention Center, modestly call it the Center of the Engineering Universe. In truth, they may not be so far off.
The show used to be Embedded Systems, parts of which still survive therein, but now it’s really so much more. Design West today includes tracks entitled Android, Black Hat, DesignMED, Designing with LEDs, Multicore, and Sensors in Design – some of which used to be shows in themselves. Now they’re all living side-by-side under one Big Top, and seeming to enjoy the synergy.
Design West is underway this week at the San Jose Convention Center. There are plenty of people in attendance, both in the sessions and in the Exhibit Hall, particularly at the Intel booth.
Intel’s a popular destination at the show, because they’ve got on display there a very interesting thing.
First shown at last fall’s Intel Developers Conference, it’s a musical ensemble that plays when a swarm of several thousand 1″ pellets fly up and out of various hoppers and dispensers and land on the music-making parts of the Rube-Goldberg-like contraption.
The resulting 3-minute concert is captivating from a musical point of view, and fascinating from an engineering point of view. You can see several clips of the performance below.
All of us in EDA know and know of Graham Bell, head honcho of EDA Café and notorious video chronicler of EDA. Liz and I often wonder, “who hasn’t Graham interviewed on video?”
Well, we were able to grab the microphone (after a little jostling for the mike) and camera and ask Graham what he thought was happening in EDA and with EDA media these days.
Here’s what he had to say.
I came across Peter Rohr’s book on Hard IP, an introduction to increasing ROI for VLSI Chip designs and thought it would be a good addition to the online books we have at EDACafe.com. With help from Colby Zelnik, at Sagantec, I contacted Peter and he generously agreed to let the entire book be scanned and published on EDACafe.com. Here below is a copy of the Preface to the book and introduces the material. I hope you find it interesting and useful.
A clear indication of the pervasiveness of electronics in today’s world was the concern over impending worldwide disasters caused by breakdowns in interlinked electronic systems, due to a one digit change in the calendar from 1999 to 2000. Today’s complex VLSI chips are at the heart of this extreme level of dependence.
In terms of the requirements for electronic systems, whose uses range from communications to air traffic control, from security to consumer goods, there are constant demands for more speed, more functionality, more sophistication. Almost all of these demands are linked to faster, more complex VLSI chips.
Of course, this tremendous need for more complex chips can not be easily met. In fact, there is a great deal of talk about the necessity for a significant increase in productivity to design chips faster and inexpensively enough to meet the needs of hi-tech industries. Considering current consumers’ love affair with any kind of hi-tech gadgets, there is only one way for these demands to go – up!
In January of 2011 I began the publication of a newsletter “Assembling the Future”. With its March 2012 issue all readers of EDACafe can now access the newsletter for free. Each month I will write a blog that describes the contents of that particular edition. Just follow the link provided by EDACafe. If you lose it then use this one: http://www.gabeoneda.com/newsletter.
This month’s topic is Intellectual Property (IP) and its necessary companion verification IP (VIP). The first article written by Josh Lee of Uniquify presents a short history of the IP business, from its wild west origins to the still developing present days. The second article, by David Hsu of Kilopass describes the relative large VIP package necessary to verify non-volatile memory (NVM) had macro IP. Finally Neill Mullinger of Synopsys introduces the company’s new VIP family based on the VIPER architecture.
Next month’s topic is EDA standards. How they are developed, why we need them, and what is on the horizon. To contribute an article contact me at email@example.com.
A few thoughts about IP
The IP market needs not just IP cores, but also VIP functions and procedures, a way to find products, and standard procedures both commercial and technical.
The beginning of the IP market practically coincides with the commercial availability of logic synthesis. In the late eighties and early nineties, Synopsys introduced a package of synthesizable basic logic modules called Designware while at the same time HDL Systems also started selling synthesizable cores written in both Verilog and VHDL. HDL Systems later was assimilated by Philips semiconductors, victim of managerial incompetence. But Synopsys persisted and leveraging its large installed base of Design Compiler grew its IP business to a very lucrative and growing business. Its latest offering is based on the VIPER architecture described in this month’s issue of the newsletter.
John Fiela from CapeSym presents integration of SYMMIC thermal simulation software with Microwave Office from AWR. AWR’s Microwave Office high-frequency design platform and CapeSym’s easy-to-use SYMMIC templates produce unique and unparalleled electrical-thermal MMIC co-design of high-power RF components.
When we last left our hero – that is, Mentor’s Catapult C high-level synthesis tool – it had just been sold off to Calypto in a move that the companies said, “will create a better integrated ESL hardware realization flow.”
Now, some 7 months into the adventure, I spoke with Calypto’s recently appointed VP of Marketing Shawn McCloud at DVCon:
Shawn: Calypto specializes in the ESL hardware implementation flow. We’re accelerating design with Catapult, optimizing the design for power efficiency with PowerPro, and doing verification with SLEC, which provides equivalence checking from RTL-to-RTL, or from C-to-RTL.
Q: Who’s the competition?
Shawn: Nobody has all 3 of these products, but within high-level synthesis, it’s Forte – and yes, we are the new Mentor. For power, the competition is Apache and Atrenta, but they’re both manual solutions, while we’re automated. And, nobody has our equivalence checking capability.
Q: Your exit strategy?
Shawn: Our goal is to grow 25-to-30%, year over year, and then we will have a number of different options: acquisition, or even an IPO.
Eric Huang demonstrates a Synopsys USB 3.0 Host, Device, and PHY IP running real USB 3.0 traffic at the fastest speeds ever recorded.
The demonstration runs on HAPS FPGA-Based Prototying platform (HAPS51) with a USB 3.0 xHCI Host on Windows 7 with MCCI drivers. The Device uses Linux to implement a mass storage design. It’s super fast, because we use a RAM disk (not an SSD or HDD) for storing the data so it shows the USB 3.0 Digital IP and PHYs can really move data. It’s the fastest USB IP in the universe according to Synopsys.
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