May 3rd, 2012
The Sophia Antipolis Microelectronics Forum takes place every fall in the ‘Silicon Valley’ of Southern France, Sophia Antipolis, 5 miles inland from the beautiful Mediterranean city of Antibes.
Sophia Antipolis is about 20 minutes from the International Airport at Nice, with offices for approximately 800 high-tech companies – included among them: ARM, Broadcom, Cadence, HP, IBM, Infineon, Intel, Mentor Graphics, Nvidia, STMicro, and Synopsys – housed in a range of buildings set among the rolling hills of the enclave. Within that forested place and 800 enterprises, almost 40,000 people are employeed. There are also two college campuses in Sophia Antipolis, as well as restaurants, a golf course, multiple hotels, and a tennis institute.
In other words, if you’ve never been to the Cote d’Azur, never been to Nice or Antibes, if you think you’d love vistas across the wide blue Mediterranean Sea, want to learn more about good food, wine, Picasso, Matisse, ancient Greeks, the French Riviera, or microelectronics – and not necessarily in that order – you’re going to be wanting to go to the Sophia Antipolis Microelectronics Forum taking place this year on October 2nd & 3rd.
For the last few years, the world of Imec Senior Scientist and R&D Team Leader Firat Yazicioglu has revolved around IC design of mixed-signal and analog devices, specifically those used for bio-medical health monitoring, and not just the technical challenges, but the economic and ergonomic aspects as well.
When we spoke recently, Firat said, “At Imec [in Leuven, Belgium] we are looking at all pieces of the puzzle with regards to bio-medical devices. How can you curb the costs, what are the details of the electronics, and how can a wearable sensor offer a solution to the problem of home monitoring for patients with chronic disease? Things like arrhythmia or predicting a seizure before it happens.
“These questions are definitely More than Moore issues that involve both digital and analog content on-chip, signal processing problems, and the need for such devices to run on very, very low power.
Author: David Yeh
Director, Integrated Circuit and Systems Sciences
Semiconductor Research Corporation
Chair of the CEDA Awards Committee
Our EDA industry is made of many talented and creative individuals, many of whom are members of IEEE and participate in CEDA’s activities. I hope you’ll be able to join us as we honor some of them with achievement awards during the opening session of DAC Tuesday, June 5, at the Moscone Center in San Francisco. We will also recognize three members of our community who are newly appointed Fellows of the IEEE.
The awards are the Donald O. Pederson for the best paper of IEEE Transactions on Computer-Aided Design, the A. Richard Newton Technical Impact, the Outstanding Service Contribution and the Phil Kaufman.
Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.
By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.
The topics covered in this report are:
- Survey methodology and demographics
- Top methods used to reduce power
- Percent of engineering time spent meeting power specifications
- Top criteria for selecting RTL power optimization tools
- Process nodes where RTL power optimization becomes important
- Plans to implement power optimization tools in 2012
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