EDACafe Weekly Review November 6th, 2014

Kaufman Dinner: Philosophy redefined
November 6, 2014  by Peggy Aycinena

 

It was impossible not to be in a celebratory mood if you attended the exuberant Kaufman Award dinner at the San Jose Marriott on Tuesday, November 4th, honoring this year’s nominee, Dr. Lucio Lanza. Next door to the Kaufman ballroom, where at least 250 well-dressed pillars of the EDA industry were eating, drinking, and reconnecting with old friends, was another ballroom where hundreds and hundreds more were celebrating early election results for one of the two mayoral candidates for San Jose, elections having been held that day. Combining the energies emanating from the two ballrooms, the whole hotel was really rocking.

If Your Chip Is Not an SoC, It Soon Will Be
November 5, 2014  by Tom Anderson, VP of Marketing

Last week’s post was addressed primarily to those of you who are already designing SoCs. We made the point that more and more SoCs have multiple processors, either homogenous or heterogeneous, and that most or all of those processors do or will have caches. This led to the main conclusions of the post, that multi-processor cache coherency is necessary for most SoCs, and therefore that coherency is now a problem extending beyond CPU developers to many chip-level verification teams.

But what if you don’t have embedded processors in your design? There’s a clear sense emerging in the industry that more and more types of chips are becoming multi-processor SoCs, and most of these will require cache coherency for the CPU clusters and beyond. In this post we’ll describe the trends we see, based in part on what we learned at the recent Linley Processor Conference in Santa Clara. The world as we know it is changing rapidly, offering more challenges for verification teams but more opportunities for us to help.

Introduction

USB-3-1-vs-USB-3-Technical-ComparisonInitially, USB provided two speeds (12 Mbps and 1.5 Mbps). With rapid adoption and success of the USB standard and the increasing power of PCs and computing devices, the USB 2.0 specification was defined in the year 2000. USB 2.0 provided upto 480 Mbps of bandwidth while keeping software compatibility with earlier USB applications. With ever increasing bandwidth requirements, in 2008 the USB 3.0 specification (providing 5 Gbps bi-directional bandwidth) was released. USB 3.1 is the next logical step in this progression. It provides 10Gbps of bi-directional bandwidth while maintaining backward compatibility with previous USB versions. To know more about USB 3.1 Verification solution click here.

In this post, we will analyze the technical differences between the USB 3.1 and USB 3.0 specifications. The aim is to enable people familiar with USB 3.0 to quickly understand the main aspects of USB 3.1.

 We will analyze the PHY, Link and Protocol layers and list out the major ways in which USB 3.1 differs from USB 3.0.



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