EDACafe Weekly Review February 22nd, 2018

Despite increasing costs of development, IC manufacturers are still making great strides.

The success and proliferation of integrated circuits has largely hinged on the ability of IC manufacturers to continue offering more performance and functionality for the money. Driving down the cost of ICs (on a per-function or per-performance basis) is inescapably tied to a growing arsenal of technologies and wafer-fab manufacturing disciplines as mainstream CMOS processes reach their theoretical, practical, and economic limits. Among the many levers being pulled by IC designers and manufacturers are: feature-size reductions, introduction of new materials and transistor structures, migration to larger-diameter silicon wafers, higher throughput in fab equipment, increased factory automation, three-dimensional integration of circuitry and chips, and advanced IC packaging and holistic system-driven design approaches.

For logic-oriented processes, companies are fabricating leading-edge devices such as high-performance microprocessors, low-power application processors, and other advanced logic devices using the 14nm and 10nm generations (Figure 1). There is more variety than ever among the processes companies offer, making it challenging to compare them in a fair and useful way. Moreover, “plus” or derivative versions of each process generation and half steps between major nodes have become regular occurrences.

For five decades, the industry has enjoyed exponential improvements in the productivity and performance of integrated circuit technology. While the industry has continued to surmount obstacles put in front of it, the barriers are getting bigger. Feature size reduction, wafer diameter increases, and yield improvement all have physical or statistical limits, or more commonly…economic limits. Therefore, IC companies continue to wring every bit of productivity out of existing processes before looking to major technological advances to solve problems.

The growing design and manufacturing challenges and costs have divided the integrated circuit world into the haves and have-nots. In the June 1999 Update to The McClean Report, IC Insights first described its “Inverted Pyramid” theory, where it was stated that the IC industry was in the early stages of a new era characterized by dramatic restructuring and change. It was stated that the marketshare makeup in various IC product segments was becoming “top heavy,” with the shares held by top producers leaving very little room for remaining competitors. Although the Update described the emerging inverted pyramid phenomenon from a marketshare perspective, an analogous trend can be seen regarding IC process development and fabrication capabilities. The industry has evolved to the point where only a very small group of companies can develop leading-edge process technologies and fabricate leading-edge ICs.


Figure 1

ESD Alliance, 11 Member Companies at DVCon in San Jose Next Week
February 19, 2018  by Bob Smith, Executive Director

San Jose should be hopping next week as chip design verification enthusiasts from all over arrive for the annual DVCon conference and exposition that runs Monday through Thursday, February 26-March 1, at the DoubleTree Hotel.

If you plan to attend, stop by our tabletop in the foyer directly across from the entrance to the exhibit area. You can find out about the ESD Alliance’s charter, programs, initiatives and ongoing events. Exhibitors and attendees can pick up copies of its latest newsletter and giveaways for members and companies interested in joining.

While Monday’s a full day of tutorials, attendees will stick around for the DVCon Expo and Reception that will be held from 5 p.m. until 7 p.m. The exhibit floor is open Tuesday, February 27, and Wednesday, February 28, from 2:30 p.m. until 6 p.m. as well. The tutorial program continues Thursday.

Attendees will find a good number of our members on the exhibit floor. They include:

Altair Engineering, Booth #404

AMIQ EDA, Booth #405

Blue Pearl, #701

Breker Verification Systems, Booth #304

Cadence, Booth #702

Mentor, a Siemens Business, Booth #1101

OneSpin, Booth #902

Real Intent, Booth #402

Sigasi, Booth #601

Synopsys, Booth #101

Verific, Booth #505

Many of these same companies will offer presentations, tutorials, lunches and collocated events, and may be part of the poster sessions. One or two will be represented on one of Wednesday’s panels. Synopsys’ Christopher Tice will give the keynote titled, “Industry’s Next Challenge: The Petacycle Challenge.” That will be held Tuesday at 1:30 p.m.

DVCon is sponsored by the industry initiative Accellera. Exhibits-only registration is free and includes the keynote and panels. For details on the full-conference registration, go to the DVCon website at: www.dvcon.org

We look forward to seeing you at DVCon and, if your company is not a member, we welcome the chance to explain why your company should join the ESD Alliance. If you won’t be at DVCon this year, please visit the ESD Alliance website to read about our committees and other ongoing initiatives, or contact me for more specifics on ROI or other justifications for joining. I can be reached at bob@esd-alliance.org

Engage with the ESD Alliance at:

Website: www.esd-alliance.org

ESD Alliance Bridging the Frontier blog: http://bit.ly/2oJUVzl

Twitter: @ESDAlliance

LinkedIn: https://www.linkedin.com/groups/8424092

Facebook: https://www.facebook.com/ESDAlliance

Intel far surpasses others with R&D spending of $13.1 billion in 2017 and accounts for 36% of expenditures among Top R&D spenders.

The ten largest semiconductor R&D spenders increased their collective expenditures to $35.9 billion in 2017, an increase of 6% compared to $34.0 billion in 2016. Intel continued to far exceed all other semiconductor companies with R&D spending that reached $13.1 billion. In addition to representing 21.2% of its semiconductor sales last year, Intel’s R&D spending accounted for 36% of the top 10 R&D spending and about 22% of total worldwide semiconductor R&D expenditures of $58.9 billion in 2017, according to the 2018 edition of The McClean Report that was released in January 2018. Figure 1 shows IC Insights’ ranking of the top semiconductor R&D spenders, including both semiconductor manufacturers and fabless suppliers.


Figure 1
Intel’s R&D expenditures increased just 3% in 2017, below its 8% average annual growth rate since 2001, according to the new report. Still, Intel’s R&D spending exceeded the combined R&D spending of the next four companies—Qualcomm, Broadcom, Samsung, and Toshiba—listed in the ranking.

DownStream: Solutions for Post Processing PCB Designs


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