September 7th, 2016
Nothing is forever in life, most things are fleeting. And such is certainly the case for the giddy, glory days of EDA at the end of the last millennium when the likes of Abbie Kendall and Jean Armstrong ran the show — the PR show, that is, for Cadence at the height of the Ray Bingham Era.
The DAC of 1999 has already been memorialized here, in and around an homage to the late, great Marie Pistilli – but the DAC of 2000, at least the Cadence version, was even grander.
The night Cadence took their Press & Analyst constituency out on the town in June of 2000 was almost beyond belief. Remember that something like 11,000 hearty souls were on board in Los Angeles for DAC that year, the conference ramping up for the week at Staples Center just as the previous week’s Exotic Erotica Show was winding down. How appropriate.
Big money was flowing everywhere within the EDA ecosystem and the Big Players needed to demonstrate in the showiest way possible that theirs was the one that was going to dominate the next decade, theirs was the enterprise that was going to win the war.
DVCon India Kicks-Off Fall Season
September 6, 2016 by Lauro Rizzatti
DVCon India could be considered the official start of the fall season for our industry. It kicks off Thursday, September 15, and runs through Friday, September 16, at The Leela Palace in Bangalore, an elegant hotel and a great place to host a content-rich technical event like this.
The two-day event, now in its third year, will offer a bit of technical everything for design and verification engineers and engineering managers, from keynotes and panels to tutorials and papers. I hope to see an increment in attendance from about 650 in 2016. The attendees will have the opportunity to take part in many of the informal technical discussions. It’s a great networking opportunity.
One not-to-be missed keynote, “Design Verification: Challenging Yesterday, Today and Tomorrow,” will be delivered by Mentor Graphics’ Wally Rhines. According to the abstract found on the DVCon India website, he will review the major phases of the verification evolution over the past several decades and focus on the challenges of newly emerging problems. I’m looking forward to his insights and expect to see some terrific visuals.
As I did last year, I will moderate a panel titled, “The Future Verification Flow,” the first day from 12:10 p.m. until 1 p.m. in the Grand Ballroom. Panelists will be Mike Bartley of Test and Verification Solutions (T&VS), Shankar Narayana Bhat who hails from Qualcomm’s Bangalore Design Centre and Ashish Kumar who will join us from the Broadcom India Design Centre.
We plan on a lively discussion as we review the challenges of the current verification flows and hash over whether emulation will become the de facto verification tool replacing simulation and, if so, the kind of disruption it could create. We intend to take a hard look at emulation versus simulation in the verification flow and determine the effectiveness of a simulation/formal verification flow versus a simulation/emulation flow. I’m planning to put each panelist on the spot and ask them to predict what’s coming next in the continuing evolution of verification.
Descriptions of all the technical sessions, papers and tutorials, make them all seem interesting and thought-provoking, but one in particular stands out for me. It’s the ESL Tutorial: Hybrid Solution Combining Emulation and Virtual Prototyping. That’s high on my “Must See” list.
And then, there is the exhibit floor. The big three –– Cadence, Mentor and Synopsys –– will have booths, as will Verific, Aceic Design Technologies, Breker Verification Systems, Dassault Systemes, Doulos, Magillem, NEC, Real Intent, SmartDV Technologies, T&VS and True Chip.
This year’s DVCon India should be as much of a standout event as it was last year. For more information, visit: https://dvcon-india.org/
My next blog post will be a trip report on DVCon India. Look for it later in September.
What Keeps You Awake at Night?
September 5, 2016 by Bob Smith, Executive Director
While many things keep me awake at night, concerns about IP tracking and security must keep many chip project managers from getting a restful sleep. That’s what convinced Warren Savage, chair of the ESD Alliance’s Semiconductor IP Working Group and general manager of Silvaco’s IP Division, to organize a panel “Semiconductor IP Issues that Keep You Up at Night.” It will be held Wednesday, September 14, from 6 p.m. until 8:30 p.m. at Silvaco’s offices in Santa Clara, Calif. Light snacks and beverages will be served during the networking hour from 6 p.m. until 7 p.m.
Warren will start the evening with an overview of the IP landscape. A panel will follow with experts Eric Stein from PwC and Rob Ballow of KPMG, who will share their advice on best practices, offer ways to implement them and answer audience questions. Eric and Rob are leading authorities on IP compliance from two of the largest worldwide auditing firms.
According to Warren, the massive amount of IP reuse involved in building an SoC has created a “big data” problem that is poorly managed by industry standards or methodologies. Instead, IP companies face a situation where their IP may be used without the proper license, leading to millions of dollars of lost revenue. Semiconductor companies face different issues but equally troubling as their engineers may inadvertently expose them to potentially huge liabilities as a result of “accidentally” reusing a core without the proper license. Warren, Eric and Rob will outline commonly used practices used today and discuss new technologies that may help both buyers and sellers rest easier.
This event is open to all ESD Alliance member companies free of charge. Non-ESD Alliance members are welcome to attend at a cost of $40, payable online or at the door. For more information, click here. To register, click register.
As an expert in IP design and reuse, Warren worked with the Alliance to form the Semiconductor IP Working Group, our newest initiative. The group is working on a common methodologies and best practices for fingerprinting, and an end-to-end solution for tracking and auditing soft and hard IP that benefits both IP developers and vendors as well as IP users.
As I mentioned in several earlier blog posts, please contact me if your company is considering joining the ESD Alliance. Member companies will be eligible to receive information from or participate in the SIP Working Group’s efforts. Additionally, employees of member companies can participate in the SIP Working Group or some of the other initiatives offered by the Alliance. I’m always available to answer any questions about the Alliance and why your company should join. Please contact me at firstname.lastname@example.org.
Join us September 14 and have a better night’s sleep! We look forward to seeing you. For more information about the ESD Alliance, visit: www.esd-alliance.org.
Hitting the Town with DVClub
September 1, 2016 by Tom Anderson, VP of Marketing
For those unfamiliar with the idiom, “hitting the town” or “going out on the town” means heading out to make the rounds of bars, restaurants, theaters, clubs, etc. It’s usually used in a city where such entertainment options abound. The topic of today’s post on The Breker Trekker blog is a particular club, DVClub, that packs in plenty of solid technical information along with entertainment. You may not have to go far to hit one; a DVClub event is likely to be coming to your city soon.
The history of the Design Verification Club (DVClub) is quite interesting, stretching back more than ten years. It started as an informal event for verification engineers to get together to share stories and talk about new technologies to help them do their jobs. You might have noticed that, unlike DVCon, the title means “design verification” and not “design and verification.” This gathering is intended for semiconductor functional verification engineers.
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