EDACafe Weekly Review November 16th, 2016

Choosing an embedded operating system
November 15, 2016  by Colin Walls

I was recently approached for help by a Mentor Graphics customer, who was planning a new project and needed to select an operating system. They wanted guidance with that choice. Of course, one is tempted to say that it does not matter which of our products they chose (as, between them, Nucleus RTOS and Mentor Embedded Linux do cover most possibilities), but I felt they needed something more objective.

There is actually a huge choice. Given that it is decided to purchase an OS, instead of developing something in-house (an expensive option which rarely makes sense), there is the choice between the “heavyweight” OSes, like Windows CE and various flavors of Linux, and around 200 other, mostly real time (RTOS), products. What the customer was after was a simple decision driven process, like a flowchart …

An Easier Path to Faster C with FPGAs
November 14, 2016  by Zibi Zalewski, General Manager, Hardware Division

For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer.

More and more, the general-purpose processor found in server-class platforms is yielding to something more optimized for the challenges of high-performance computing (HPC). Advanced algorithms like convolutional neural networks (CNNs), real-time analytics, and high-throughput sensor fusion are quickly overwhelming traditional hardware platforms. In some cases, HPC developers are turning to GPUs as co-processors and deploying parallel programming schemes – but at a massive cost in increased power consumption.

A more promising approach for workload optimization using considerably less power is hardware acceleration using FPGAs. Much as in the early days of FPGAs where they found homes in reconfigurable compute engines for signal processing tasks, technology is coming full circle and the premise is again gaining favor. The challenge with FPGA technology in the HPC community has always been how the scientist with little to no hardware background translates their favorite algorithm into a reconfigurable platform.

As I recently shared, UVVM, VHDL’s long-awaited alternative to UVM, promises to be interesting. Later this week, I’ll be joined by Espen Tallaksen, Bitvis Managing Director and Founder for a joint webinar, UVVM – A game changer for FPGA VHDL Verification.

Below, please find Espen Tallaksen’s recent guest blog on the topic that originally appeared on the Aldec Blog.

FPGA VHDL Verification
How can we do this faster and with better quality – at no extra cost?
by Espen Tallaksen, Bitvis Managing Director and Founder

This is actually possible – and with an average efficiency improvement of 20 to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost.

 All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good top level design architecture is critical. Most FPGA designers also know that a good microarchitecture is at least as important for module design. It should thus be obvious that a good architecture is also equally important for your testbench, but for some strange reason most testbenches do not have the same good architecture as the design being verified.

Most designers agree that the following are critical for an efficient development of a high quality design module:

–          Overview, Readability, Simplicity

–          Modifiability, Maintainability, Extendibility

–          Debuggability

–          Reusability

So why should testbenches be any different, with on average the same time usage as the actual design?

 


If you were watching Seattle beat New England last night
, and not the news, you missed it: The rumor that Munich-based Siemens would buy Wilsonville-based Mentor Graphics.

This morning, of course, it’s no longer a rumor. The players themselves have announced that the deed is done.

Per the Press Release, “Siemens and Mentor Graphics today announced that they have entered into a merger agreement under which Siemens will acquire Mentor for $37.25 per share in cash, which represents an enterprise value of $4.5 billion.”

Wow, talk about just in the nick of time.

DAC 2017: Deadlines for IP Submissions start November 15th
November 10, 2016  by Peggy Aycinena

 


Next Tuesday, November 15th, is the deadline
for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

#54 DAC, 2: Executive committee members you need to know (and your first slate of deadlines)
November 10, 2016  by Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IP

Time is the only critic without ambition. – John Steinbeck

Like many things, DAC looks decidedly different depending on where you sit, and how you experience it.  As an attendee, it’s mostly a few days at the start of every summer where you can sample some of the best technical content on the design of circuits and systems, plus get the chance to network and have some fun with a worldwide audience that spans execs to undergrads. In contrast, as a member of the executive committee, DAC is the finish line for a year-long marathon effort to bring the best content, speakers and papers all together in one place and time, building on what works and improving where we can.

Now is the time for a reminder that if you want present a paper at DAC (especially a research paper), the 12-month calendar matters for you as well. Abstracts are due Nov. 15; manuscripts, Nov. 22!       ­

 


The American people have spoken
and the electoral college will finalize the results shortly. The new President-elect is someone who has ridden into office on a tidal wave of enthusiasm for his professed commitments to a reduction in globalization, more tightly controlled borders, bringing off-shored jobs back home to citizens who deserve to have them, and a carefully articulated affection for nativism.

EDA is in trouble on all counts.

First of all, the EDA industry, and its associated fortunes, have been built on a powerful foundation of globalization; prominent members of the industry have quite literally lobbied long and hard to be sure that stays the case.

Mentor CEO Dr. Walden C. Rhines has, in fact, been honored multiple times by the industry’s consortium for his extraordinary leadership in helping to guarantee that EDA software is not unduly constrained by export restrictions, licensing inhibitions, or government nay-sayers.

CST Webinar Series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IOTPLL


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